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AR008437A1 - Co-procesador de filtro, metodo para decodificar una senal modulada ortogonalmente, un receptor que lo comprende y ecualizador para su uso en dichoreceptor - Google Patents

Co-procesador de filtro, metodo para decodificar una senal modulada ortogonalmente, un receptor que lo comprende y ecualizador para su uso en dichoreceptor

Info

Publication number
AR008437A1
AR008437A1 ARP970104282A ARP970104282A AR008437A1 AR 008437 A1 AR008437 A1 AR 008437A1 AR P970104282 A ARP970104282 A AR P970104282A AR P970104282 A ARP970104282 A AR P970104282A AR 008437 A1 AR008437 A1 AR 008437A1
Authority
AR
Argentina
Prior art keywords
processor
filter
dichoreceptor
ortogonally
equalizer
Prior art date
Application number
ARP970104282A
Other languages
English (en)
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of AR008437A1 publication Critical patent/AR008437A1/es

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/30—Time-delay networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Power Engineering (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Complex Calculations (AREA)
  • Filters And Equalizers (AREA)
  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
  • Facsimile Image Signal Circuits (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Hydrogenated Pyridines (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
  • Preparation Of Compounds By Using Micro-Organisms (AREA)
  • Advance Control (AREA)

Abstract

Un co-procesador de filtro (Fig.1) dentro de un Procesador de Senales Digitales (DSP) aprovecha la naturaleza ortogonal de las senales moduladasdurante el proceso de ecualizacion. Dado que, después de la recepcion, solo ciertos valoresreal es/imaginarios de la senal recibida son utiles para ladesmodulacion, el co/procesador de filtro (fig1) solo procesa esos valores para estimar la senal transmitida. Mediante el procesamiento de solo esos valoresutiles para la desmodulacion, elco-proc esador de filtro (fig.1) puede procesar más informacion en un tiempo dado, produciendo el aumento del procesamientocomparado con el arte previo.
ARP970104282A 1996-10-04 1997-09-18 Co-procesador de filtro, metodo para decodificar una senal modulada ortogonalmente, un receptor que lo comprende y ecualizador para su uso en dichoreceptor AR008437A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/725,871 US5905757A (en) 1996-10-04 1996-10-04 Filter co-processor

Publications (1)

Publication Number Publication Date
AR008437A1 true AR008437A1 (es) 2000-01-19

Family

ID=24916302

Family Applications (1)

Application Number Title Priority Date Filing Date
ARP970104282A AR008437A1 (es) 1996-10-04 1997-09-18 Co-procesador de filtro, metodo para decodificar una senal modulada ortogonalmente, un receptor que lo comprende y ecualizador para su uso en dichoreceptor

Country Status (17)

Country Link
US (1) US5905757A (es)
JP (1) JP4494531B2 (es)
KR (1) KR100306014B1 (es)
CN (1) CN1153422C (es)
AR (1) AR008437A1 (es)
AU (1) AU3587597A (es)
CA (1) CA2238299C (es)
DE (1) DE19781047B4 (es)
ES (1) ES2147693B1 (es)
FI (1) FI117493B (es)
FR (1) FR2754366B1 (es)
GB (1) GB2322057B (es)
IT (1) IT1295391B1 (es)
RU (1) RU2178949C2 (es)
SE (1) SE517510C2 (es)
TW (1) TW340285B (es)
WO (1) WO1998015056A1 (es)

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DE10003006A1 (de) * 2000-01-25 2001-07-26 Bosch Gmbh Robert Anordnung und Verfahren zur Signalverarbeitung und Speicherung
DE10127348A1 (de) * 2001-06-06 2002-12-19 Infineon Technologies Ag Verfahren und Schaltungsanordnung zur Übertragung von Daten zwischen einem Prozessor und einem Hardware-Rechenwerk
EP1297668B1 (de) * 2000-07-03 2005-11-16 Infineon Technologies AG Viterbi-entzerrer der verschiedene hardware-datenpfade für acs-operationen und für übertragungsmetriken verwendet
US6873662B2 (en) * 2002-02-14 2005-03-29 Interdigital Technology Corporation Wireless communication system having adaptive threshold for timing deviation measurement and method
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RU2242792C2 (ru) * 2002-04-29 2004-12-20 Открытое акционерное общество "Краснодарский ЗИП" Способ быстрой усредняющей ких-фильтрации на основе процессора
US7428278B2 (en) * 2002-05-09 2008-09-23 Interdigital Technology Corporation Method and apparatus for parallel midamble cancellation
US7222288B2 (en) 2004-07-30 2007-05-22 Hellosoft, Inc. Modified soft output Viterbi algorithm for truncated trellis
US7492839B2 (en) * 2004-07-30 2009-02-17 Hellosoft Inc. Efficient implementation of GSM/GPRS equalizer
ES2302638B1 (es) * 2006-12-21 2009-06-04 Vicente Diaz Fuente Metodo mejorado de codificacion y decodificacion con al menos dos pares de secuencias ortogonales.
US8560760B2 (en) * 2007-01-31 2013-10-15 Microsoft Corporation Extending flash drive lifespan
US7657572B2 (en) 2007-03-06 2010-02-02 Microsoft Corporation Selectively utilizing a plurality of disparate solid state storage locations
KR101715709B1 (ko) * 2009-07-07 2017-03-13 코닌클리케 필립스 엔.브이. 호흡 신호들의 잡음 감소
US10175980B2 (en) 2016-10-27 2019-01-08 Google Llc Neural network compute tile
US10360163B2 (en) 2016-10-27 2019-07-23 Google Llc Exploiting input data sparsity in neural network compute units
CN109120241B (zh) * 2017-06-23 2022-03-22 北京遥感设备研究所 一种实数交叉型复系数fir滤波器
CN109564684B (zh) * 2018-01-15 2023-05-02 深圳鲲云信息科技有限公司 图像语义分割方法、可编程逻辑电路、系统及电子设备

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Also Published As

Publication number Publication date
DE19781047T1 (de) 1998-12-17
SE9801958L (sv) 1998-08-03
ES2147693B1 (es) 2001-05-16
GB2322057B (en) 2001-04-25
FR2754366A1 (fr) 1998-04-10
FI117493B (fi) 2006-10-31
KR100306014B1 (ko) 2001-11-02
TW340285B (en) 1998-09-11
FI981263A7 (fi) 1998-06-03
DE19781047B4 (de) 2005-09-29
GB9811085D0 (en) 1998-07-22
KR19990071907A (ko) 1999-09-27
ITRM970553A1 (it) 1999-03-15
SE517510C2 (sv) 2002-06-11
ES2147693A1 (es) 2000-09-16
CA2238299A1 (en) 1998-04-09
FR2754366B1 (fr) 2003-08-15
AU3587597A (en) 1998-04-24
JP2000501918A (ja) 2000-02-15
RU2178949C2 (ru) 2002-01-27
CN1153422C (zh) 2004-06-09
GB2322057A (en) 1998-08-12
SE9801958D0 (sv) 1998-06-03
CA2238299C (en) 2000-09-26
IT1295391B1 (it) 1999-05-12
JP4494531B2 (ja) 2010-06-30
FI981263A0 (fi) 1997-07-08
CN1205133A (zh) 1999-01-13
WO1998015056A1 (en) 1998-04-09
US5905757A (en) 1999-05-18

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