NO873059L - DOUBLE-SWITCH POWER SUPPLY. - Google Patents

Description

ABBREVIATIONS AND EXPRESSIONS:

Because the invention is intended for an international market, several parts have been given English names and abbreviations. These are explained below:

DS = Double Switched

Used for switching units with a switch in each power conductor

DSCIC = Double Switched Current Injected Capacitor

= Double switched current injected capacitor

DSP = Dual Switched Power Supply

= Double switched voltage supply

The name of the invention

DSSU = Double Switched Switch Unit = Double Switched Switch Unit

SSP = Spike Suppressor and Protector

= Surge suppressor and protector

The Dual Switching Principal

Voltage spikes or spike = Strong overvoltage of short duration

Chap. 1 DSP p

1.1 Use of DSP:

DSP is a power supply that is designed to be used in connection with sensitive analog and digital electronics that do not tolerate the noise that ordinary power supplies have on the output when they receive noise pulses on the input.

1.2 Today's technology

In many places where electronic structures are in use, high-frequency noise (RF noise) and low-frequency noise (LF noise) is a big problem.

Many types of LF noise propagate along the mains voltage lines, hereafter called the mains, and reach the output of the voltage supply.

The most common way to try to avoid this noise is by using passive LC or RC filters. Due to physical limitations of the existing components, it is impossible to build such filters that filter out all noise!

Another method is to connect an electric motor to the noisy network. The engine drives a generator which in turn is connected to a normal voltage supply. In this way, it has been possible to obtain a noise-free voltage source. The method works excellently, but is hugely space-consuming and expensive and thus inappropriate in many contexts.

1.3 Advantages of DSP:

DSP (fig. 2.0) totally suppresses both RF and LF noise:

DSP mainly consists of two DSSU (chapter 3.2) in series connection. These are switched according to a timing diagram shown in fig. 2.8, and which I have called the double switching principle "(ch. 3.1). The two switches in each DSSU are switched in parallel. The two DSSUs are again switched by a 2-phase non-overlapping clock pulse as described in 2.8 and 2.9. This constitutes the new part of the design.

This means that at no point in time is there electrical contact between the input and output of the voltage supply, and LF noise cannot thus pass through.

To filter out RF noise, I have threaded ferrite rings onto the wires in several places, used shielded wires and shielded the devices from each other. I have also introduced a common passive filter for this purpose. This constitutes the part of the design that is well-known technology.

Chap. 2 Description of block diagram :

2.0 General description:

The block diagram of the DSP is shown in fig. 2.0. The purpose of the DSP design is to completely suppress noise at the input, so that the output is noise-free!

The switches in DSSU 1 are driven by the clock signal phase 1, which has "duty cycle" dl. Similarly, DSSU 2 is powered by phase 2 which has a "duty cycle" d2. See the timing diagram in fig. 2.8. This is called the double switch principle. d2 is usually much smaller than dl so that the output voltage from DSSU 1 is much larger than the output voltage from DSSU 2.

When a moderate voltage spike occurs at the mains input, the SSP suppresses most of it. If the switches in DSSU 1 are closed at this time, the rest of the spike will be transferred here, and will be extinct when the switches in DSSU 2 are closed. Thus the output of the DSP remains noise-free!

If a more extreme spike occurs on the grid, the overvoltage sensor (Fig. 2.1) in the SSP will signal the DSSU 1 to open the switches. Due to the delay built into the mains filter, DSSU 1 will be disconnected when the spike reaches the input. While DSSU 1 is disconnected, the capacitor in DSSU 1 will supply DSSU 2 with energy. This is why it is so important that the output voltage from DSSU i is much greater than the output voltage from DSSU 2. TiIbakelinkkontrol1 2 will then increase the "duty cycle" of the switching in DSSU 2 to keep the voltage at the output of DSP constant while the capacitor in DSSU 1 is discharged.

If an extreme overvoltage occurs on the mains, the surge protectors SO, Sl and S2 will short-circuit and blow the fuses, thus protecting the output electronics from being damaged.

Known noise limiting circuits from the design of "switch mode" power supplies will not be discussed as they are known technology.

2.1 SPS:

The SSP (fig. 2.1) consists of a fuse in each mains cable and 3 surge protectors called SO, Sl and S2. They can be of the gas discharge type, or faster say 1 icon based units. This provides "common mode" and "differential mode" overvoltage protection. If the circuit is exposed to a high overvoltage, the overvoltage protectors will short-circuit and blow the fuses.

Small coils with a few windings in each of the mains cables are also mounted. In addition, a varistor and two zener diodes are mounted in parallel with the mains cables.

The knee voltage of the varistor must be lower than the knee voltage of the two zener diodes which are equal. This is done because the varistor can absorb more energy than the zener diodes without being damaged, but the zener diodes are much faster than the varistor.

When a voltage spike reaches the knee voltage of the varistor, it starts to conduct. If the rise time of the spike is very short, the varistor will only just begin to conduct, and the voltage across it will continue to rise until it reaches the knee voltage of the zeners. The zener diodes will limit the voltage to this high frequency voltage peak for the short time it takes for the varistor to start conducting completely. The Zener diodes will therefore absorb only a small amount of energy.

Finally, a nail sensor is fitted that detects overvoltages of longer duration, and signals DSSU 1 through an optocoupler to disconnect from the grid while the nail dies out.

2.2 The net filter:

The mains filter (fig. 2.0) is a common "common mode" and "differential mode" filter that is impedance-matched. It will not be described here as it is well known technology.

The filter also acts as a delay network. This gives the SSP time to signal DSSU 1 to open switches SIA and S1B when a spike occurs.

2.3 The transformers:

Transformers 1 and 2 (fig„ 2.0) can be looped depending on how the DSP is realised. If used, they must be of the shielded type with shielded primary and secondary windings. The screen closest to the primary must be grounded to mains earth, and the screen closest to the secondary must be grounded to minus. The transformer must again be enclosed by a shield.

2.4 The rectifiers:

The rectifiers (fig. 2.0) and any diodes in the switching units DSSU 1 and DSSU 2 must consist of so-called "fast recovery" or "schottky" diodes. In this way, the rectifiers generate as little noise as possible.

2.5 DSSU:

A general DSSU is shown in fig. 2.2. It consists of two switches SIADg S1B, one in each voltage conductor. The switches operate in parallel, After the switches there is a so-called switching element. The task of the switching element is to transform the 1-pole voltage Vi to the 1-pole voltage Vo by regulating the "duty cycle" of the switches. After the switching element, there is a surge protector OSB which ensures that the voltage from the switching element does not exceed a certain value.

The switching element can be built in several ways, and is based on known devices from "Switch mode" voltage supplies. The surge protector can also be built in several different known ways.

This gives us several different possible configurations of the DSSU. Examples of switching elements are shown in fig. 2.3 - 2.7, and is discussed in 2.5.1 - 2.5.6.

DSSU 1 and DSSU 2 in fig. 2.0 may be the same or different. The switches in

DSSU 1 is called SIA and S1B, and the switches in DSSU 2 S2A and S2B.

2.5.1 "DS Forward Converter" switching element :

See fig. 2.3. This switching element is based on a normal "forward converter".

2.5.2."Isolated Forward Converter" switching element:

See fig. 2.4. This switching element is based on a common "Isolated Forward Converter".

In ti Hegg, the coil transformer must be of the type described in 2.3. Either SIA or S1B can be bypassed if experience shows that the isolated coil transformer provides the necessary noise protection.

2.5.3 "DS Flyback Converter" switch element :

See fig. 2.5. This switching element is based on a normal "forward converter"

2.5.4 "Isolated Flyback Converter" switching element:

See fig. 2.6. This switching element is based on a common "Isolated Flyback Converter".

In addition, the coil transformer must be of the type described

in 2.3. Either SIA or S1B can be bypassed if experience shows that the isolated coil transformer provides the necessary noise protection.

2.5.5 DSCIC:

The DSCIC (Fig. 2.6) is designed to be used as one or both DSSUs. It consists of a current source which is switched against a capacitor C via two switches SIA and S1B which operate in parallel.

2.5.6 Construction of DSSU;

A DSSU may consist of any of the switching elements discussed above, but it may also consist of any other switching element with similar characteristics. The only limitation is that the two switches SIA and S1B must operate in parallel and two DSSU must be able to be operated in series connection (fig. 2.0) of the clock signals phase 1 and phase 2 (fig. 2.7).

2.6 The filter:

The filter (fig. 2.05) can be looped depending on how the DSP is constructed. If it is used it can be either an LC or an RC filter.

How to construct the device is not discussed here, as there are many well-known ways to do this.

2.7 The E-effect distributor:

The power distributor (fig. 2.0) selects which of output 1 or 2 supplies the control electronics with power: When the DSP is first switched on, the control electronics receives power from output 2 through the power distributor. When the voltage at output 1 reaches its level, the voltage sensor triggers the power distributor to select output 1 to supply the control electronics with power.

This has been done because output 2 can contain noise which can cause the control electronics to operate incorrectly so that the switches in DSSU 1 and 2 will be closed at the same time. This will cause us to get noise pulses on output 1. By supplying the control electronics with current from output i, this problem is eliminated.

How to construct the device is not discussed here, as there are many well-known ways to do this.

2.8 Square pulse ski okka:

The clock generates a square pulse called phase 2 and has frequency f. The "duty cycle" d2 can be controlled via a separate input. In fig. 2.0 d2 is controlled by feedback control1 2.

The timing diagram for the clock and the clock divider is shown in fig. 2„8.

How to construct the device is not discussed here, as there are many well-known ways to do this.

2.9 The clock divider:

The clock divider (fig. 2.0) receives phase 2 from the clock, and generates phase 1. The "duty cycle" dl can be controlled via a separate input. In fig. 2.0 is controlled dl by feedback control 1. Rising edge to phase 1 comes time ten after falling edge to phase 2. t.t can be varied, but is usually fixed.

The output from the clock divider is thus two signals, phase 1 and phase 2 with the same frequency, but where the "duty cycle" of the signals can be controlled independently of each other.

These two clock signals are the key to the double switching principle and the isolation between input and output' of the DSP. Phase 1 controls the switches in DSSU 1, and phase 2 the switches in DSSU 2.

When a voltage spike reaches the input at the same time as the switches in DSSU 1 are closed, the spike will charge the capacitor in DSSU i to a higher voltage than normal. If the voltage becomes higher than the trigger voltage of the surge protector (fig. 2.3 - 2.6), this will start to discharge the capacitor at the output of DSSU 1.

The time delay t2 between the falling edge of phase 2 and the rising edge of phase 1 is there to give the excess charge on the capacitor in DSSU 1 time to discharge before the switches in DSSU 2 are closed.

The timing diagram for the clock and the clock divider is shown in fig. 2.8. ti and t2 must be > 0 for isolation between input and output to be maintained.

2.10 Feedback control1 1:

Feedback control 1 senses the output of DSSU 1 and controls the "duty cycle" dl to phase 1 to keep the output voltage constant. This regulation can also be achieved with forward coupling or a combination of forward and reverse coupling.

How to construct the device is not discussed here, as there are many well-known ways to do this.

2.11 Feedback control1 2:

Ti lbackcoupling control 1 2 -sensor on output 1 and controls the "duty cycle" d2 to -phase 2 -to keep the output voltage constant.

This regulation can also be achieved with forward coupling or a combination of forward and reverse coupling.

2.12 The voltage from the DSP:

The output voltage Vo from the ideal DSP with DC input voltage Vi is given by the equation.

1) Vo = Vi*dl*d2 where duty cycle = 1 = 100 '/.

Since each switching transistor has a finite resistance, each DSSLI has efficiency e. We then get:

2) Vo = Vi*e*dl*e*d2 = Vi*e<2>#dl*d2

From the timing diagram in fig. 2.8 we get:

3) dl+d2 = l-tx*f ==> d2 = l-tx*f-dl where tx = tl+t2

We put 3) into 2) and get:

4) Vo = Vi*e2*dl*(l-tx*f-dl) = Vi*e=*( (l-t>:*f )*dl-dl = )

We get Max Vo for a specific dl and d2 given by the equation:

5) dl = (l-tx*f)/2 and d2 = dl

If we assume that the factor tx*f = 0.1 or 10%, we get

dl = (1-0.D/2 = 0.45

If we also assume that the efficiency of each stage = 0.7, we get the following output voltage on output 1 (fig. 2.0):6) Vo = Vi#0.7<2>#0.45<2>= Vi*0.099 = approx. We/10

Of course, the output voltage can be higher if we use DSSUs with "step up" transformers.

Claims (1)

3.1 The double switch principle: Voltage supply called DSP (Fig. 2.0) characterized by two double-switched switching units called DSSU (Fig. 2.3T^ in series connection and switched according to the timing diagram in Fig. 2.8. Phase 1 drives the switches SIA and S1B in DSSU 1, and phase 2 drives the switches S2A and S2B in DSSU 2. SIA and S1B operate in parallel, and S2A and S2B operate in parallel. 3.2 The DSSU principle: Double-switched switching unit called DSSU (fig. 2.2) characterized by two switches SIA and S1B, one in each voltage conductor, which operate in parallel. The switches switch a switching element which thus transforms the 1 ike voltage Vi to the 1 ike voltage Vo by regulating the "duty cycle" of the switching. 3.3 SSP: Noise pulse suppressor called SSP (fig. 2.1) characterized by a fuse in each voltage conductor, three overvoltage protectors SO, Sl and S2 which provide "common mode" and "differential mode" overvoltage protection, a ferrite ring in each voltage conductor, a varistor in parallel, two series-connected later in parallel where the zeners are reversed each way and a spike sensor in parallel that detects voltage spikes with a certain duration and signals this via an optocoupler. 3.4 DSCIC: Double-switched current-injected capacitor called DSCIC (Fig. 2.7) characterized in that a current source I is switched into the capacitor C via two switches SIA and S1B which operate in parallel. On the output is an overvoltage protector which ensures that the voltage across the capacitor C does not exceed a certain value. Chap. 4 Summary . DSP (fig. 2.0) is a voltage supply that contains two switching units called DSSU (fig. 2.2) in series connection. The two DSSUs are switched every other time according to a timing diagram shown in fig. 2.S, and which is called the double switch principle. A special surge suppressor called SSP (Fig. 2.1) suppresses most of the surges at the input, and also signals DSSU 1 that it must disconnect from the power conductors in case of high surges. Each DSSU (fig. 2.2) is characterized by two switches SIA and S1B switching a so-called switching element which transforms the input voltage Vi to the output voltage Vo by regulating the "duty cycle" on the switches. SIA and S1B are operated in parallel. Possible switching elements are shown in fig. 2.3 - 2.7. A new DSSU called DSCIC (Fig. 2.6) has been invented. It is characterized by the fact that a current source I is switched into a capacitor C via the switches SIA and S1B.