NL9700008A - Subscriber equipment for digital radio communications system - Google Patents

Abstract

The system includes a device to modulate digital intermediate frequency signals with the filtered input symbols, a device to process the modulated input signals for transmission at the base station, a FIR (Finite Impulse Response) chip for FIR filtering of digital input symbols, a DIF (Digital Intermediate Frequency) chip for digital synthesising and modulation of digital intermediate frequency signals, and a processor chip for encoding the digital input tone signals and decoding of the base station output signals.

Description

Subscriber unit for a wireless digital communication system

The invention relates to a subscriber unit for a wireless digital communication system, and in particular is directed to an improved subscriber unit for wireless communication with a base station in a wireless digital subscriber communication system.

Such a subscriber unit is known from United States Patent Specification 4,825,448. A base station used with such a subscriber unit in a wireless digital subscriber communication system is described in U.S. Patent No. 4,777,633. The subscriber unit described in U.S. Patent No. 4,825,448 includes means for recoding a digital speech input signal to provide digital input symbols; means for FIR filtering of the digital input symbols; means for deriving an analog intermediate frequency input signal from the filtered input symbols; means for combining the intermediate frequency input signal with an RF carrier for radio transmission to the base station; means for demodulating an output signal received from the base station to provide digital output symbols; and means for synthesizing a digital speech output from the digital output symbols. The subscriber unit includes a baseband processor chip and a modem processor chip. Both are TMS32020 digital signal processors. The baseband processor chips perform the recoding of the digital speech input signal, the synthesis of the digital output symbols, and various baseband control functions. The modem processor chip further performs filtering of the digital input symbols based on finite impulse response (FIR filtering) and demodulation of the signal received from a second unit within the system. The modem processor chip generally functions as the main controller of the system.

The present invention provides a less expensive subscriber unit. The subscriber unit of the present invention includes means for recoding a digital speech input signal to provide digital input symbols; means for FIR filtering of the digital input symbols; means for modulating a digital intermediate frequency signal with the filtered input symbols to provide a modulated intermediate frequency input signal; means for processing the modulated input signal for transmission to the base station; means for demodulating an output signal received from the base station to provide digital output symbols; and means for synthesizing a digital speech output signal from the digital output symbols; wherein the subscriber unit comprises an FIR chip for performing the FIR filtering of the digital input symbols; a DIF chip for generating the digital intermediate frequency signal by digital synthesis and for modulating the digital intermediate frequency signal; and a single processor chip for performing the recoding of the digital speech input signal, for performing the demodulation of the output signal received from the base station, and for performing the synthesis of the digital output symbols.

The FIR chip performs the FIR filter function which was implemented by software in the modem processor of the prior art subscriber unit described above. By removing the time-consuming FIR filter transfer function from the modem processor and performing the demodulation function with the same processor that performs the baseband processing function, only one processor chip is required.

The means for generating the digital intermediate frequency signal by digital synthesis are a direct digital synthesizer (DDS) comprising means coupled to the processor chip for accumulating phase data provided by the processor chip to provide a predetermined intermediate frequency at to interpret; and means for processing the accumulated phase data to generate the digital intermediate frequency signal at the predetermined intermediate frequency. The present invention therefore adds new functionality to the subscriber unit that was not present with the prior art subscriber unit described above in that direct digital synthesis allows for extremely flexible tuning of the subscriber unit. In the prior art subscriber unit described above, tuning was limited to a finite set of channels spaced 25 kHz apart. Also, the difference between the transmit frequency and the receive frequency was fixed at 5 MHz. The DDS function of the DIF chip overcomes these restrictions, allowing other distances between the channels or between the transmit and receive frequencies to be supported with minimal or even no modification of the subscriber unit equipment.

Accordingly, the digital assembly unit provides a fully modulated digital intermediate frequency signal that can be generated by digital synthesis at any of a number of different predetermined intermediate frequencies; and high resolution frequency adjustment may be provided in the digital assembly unit to allow tracking of the frequency of the output signal received from a second unit. These two features allow the subscriber unit's radio to include only a fixed frequency LO reference and eliminates the need for an HF synthesizer. These two features also allow the primary frequency reference in the subscriber unit to be fixed, with all tuning operations performed by the digital assembly unit.

A direct digital synth is stable and easy to produce. Phase noise specifications can be met without the need for a costly and complex PLL HF synthesizer. The direct digital composition provides flexible frequency adjustment within the mid-frequency / band and provides more convenient frequency modifications for operation in other bands.

Another feature of the present invention is that the FIR chip also includes means for generating timing signals for timing the recoding operation and the operation of synthesizing the digital speech output signal by the processor chip .

However, the processor chip performs demodulation of the output signal received from the base station independently of the timing signals generated by the FIR chip. The processor chip receives the output signal according to the timing signals generated by the FIR chip and buffers the received output signal for demodulation, so that the processor chip can perform demodulation when it does not perform the recoding and synthesis operations.

The present invention can also reduce manufacturing costs by using a slow memory combination associated with the processor chip to store processing codes used by the processor chip when the codes need not be deployed with zero wait states and a fast memory coupled to the processor chip for temporarily storing processing codes used by the processor chip when the codes are used with zero wait states. Fast RAMs (just zero waiting states) and fast EPROMs with the same chip density are very expensive. In order to reduce costs, the processor codes can be stored in a slow EPROM (just one or down wait cycles), and when the procedures need to be completed with just zero wait cycles, the code can be transferred from slow memory to fast memory to get there companies to do.

Additional features of the present invention are described with respect to the description of the preferred embodiment.

The invention will be further elucidated with reference to the drawing, in which: figure 1 is a block diagram of a preferred embodiment of the subscriber unit according to the present invention, figure 2 is a block diagram of the FIR chip which is part of the embodiment which is shown in figure 1; Figure 3 is a block diagram of the DIF chip which is part of the embodiment shown in Figure 1; Figure 4 illustrates the processing tasks performed by the processor chip shown in the embodiment of Figure 1; Figure 5 illustrates the processing routines that are part of the modem processing task shown in Figure 4.

The following is a definition of abbreviations and acronyms used in this text: A / D analog to digital AGC automatic gain control AS1C application-specific integrated circuit BPSK binary phase shift modulation CCT channel control task CCU channel controller CRC cyclic redundancy control DAC digital-to-analog converter DDS direct digital synthesizer DIF digital center frequency DIP dual in-line housing DOR data output ready DPSK differential phase shift modulation DSP digital signal processing EPROM erasable readout memory

Flr finite impulse response 1/0 input / output LSB least significant bit MPT modem processing task MSB most significant bit MUX multiplexer PCM pulse code modulation PLL phase lock loop PWM pulse width modulation QPSK quadrature phase shift mod RAM random access memory RCC radio control channel RELP residual excited RX predictive receive RXCLK receive clock signal RXSOS receive start or slot SCT subscriber control task SLIC subscriber line interface circuit SPC signal processing controller SPT signal processing task SPTCTL signal processing task controller SSB transmit switch sample buffer TDM time division multiplexing TX transmit TXCLK transceiver clock VLART universal signal UART universal signal UART circuit

With reference to Figure 1, a preferred embodiment of the subscriber unit according to the present invention comprises a telephone interface circuit 10, a SLIC as well as codec circuit 11, a processor sor 12, a fast memory 13, a slow memory 14, an address decoder 15, a FIR chip 16, a DIF chip 17, a DAC 18, an A / D converter 19, a radio 20, a bell circuit 21, and an oscillator 22.

The FIR chip 16, which is an ASIC chip, is coupled to the DIF chip 17 through lines 23 and 24, to the processor chip 12 through processor bus 25 and line 26, to the A / D converter 19 through line 27, to the LSIC and the codec circuit 11 through line 29, to the radio 20 through line 30, and to the bell circuit 21 through line 31.

The telephone interface circuit 10 is coupled to a telephone 32, which converts sound waves into a speech input signal, and converts a speech output signal into sound waves.

The SLIC and the codec circuit 11 are coupled to the telephone interface circuit 1u for converting the speech input signal into a digital baseband input signal which is supplied to the processor chip 12.

In another embodiment (not shown), the processor chip is also directly coupled to a UART for otherwise receiving digital input signals directly from, and broadcasting digital output signals directly to, a digital I / O signal device.

The processor chip 12 includes a digital signal processor of the NMS320C25 type, which recodes the digital baseband input signal according to a RELP algorithm, to provide data to be transmitted, in the form of digital input symbols on the processor bus 25. Using a digital signal processor for performing an RELP algorithm is described in International Patent Application No. PCT / US 85/02168, International Publication No. WO86 / 02726, published May 9, 1986.

The FIR chip 16 subjects the digital input symbols to FIR filtering and supplies I, Q data to the DIF chip 17 via lines 24.

The DIF chip 17 interpolates the filtered digital input symbols and modulates a digital center frequency signal with the interpolated input symbols to provide a modulated digital input signal.

The DAC 18 converts the modulated digital input signal into a modulated analog input signal.

The radio 20 sends the modulated analog input signal to the base station; and receives and demodulates a modulated analog output signal from the base station.

The oscillator 22 is a free-running oscillator, which provides clock signals to the processor chip 12.

A description of the relationship between the subscriber unit and the base station is described in U.S. Patent No. 4,777,633.

The A / D converter 19 converts the demodulated received analog output signal into a digital output containing digital output symbols.

The processor chip 12 generates a digital baseband output signal from the digital output symbols by synthesis. Synthesis of RELP recoded symbols using a digital signal processor is also described in International Publication No. WO66 / 02726. The processor chip 12 further performs echo cancellation as described in U.S. Patent 4,697,216.

The SLIC and the codec circuit 11 convert the digital baseband output signal into the speech output signal provided by the telephone interface circuit on the telephone 32.

The FIR chip 16 consolidates the functionality of a circuit in a VLSI device to reduce the production cost of the subscriber unit by eliminating many discrete, medium-scale integrated components.

With reference to Figure 2, the FIR chip 16 includes a multi-loadable buffer 33, an internal decoding module 34, a receive sample buffer 35, control and status registers 36, an external address decoding module 37, a monitoring timing module 38, a receiving timing. ring module 39, a transmit timing module 40, a FIR transmit filter 42, a codec timing module 44, and a call control module 45.

The FIR chip 16 provides 45 millisecond frame marker signal generation, 11.25 millisecond slot marker signal generation, 16 kHz symbol clock signal generation, time correction circuitry, receive sample buffering, 8 kHz codec timing signal generation processor interface decoding, ring timing generation, external address decoding, and reset signal generation for the monitoring timer. The FIR chip 16 buffers two 5-bit transmission symbols at a rate of 8 kHz. The FIR chip 16 provides conversion and filtering of the transmit symbols into I and Q data symbols, each of these symbols having a width of 10 bits and the speed being 160 kHz. The I and Q data are interleaved and output to the DIF chip 17 at a rate of 320 kHz. The FIR chip 16 also buffers receive data samples at a rate of 64 kHz; and four receive data samples are read by the processor chip 12 at a rate of 16 kHz. Timing clock signals as well as timing signals are generated by the FIR chip 16 from an incoming 3.2 MHz master clock signal. The processor chip 12 is synchronized to these data rates by slot and symbol interrupts generated by the FIR chip 16. The 8 kHz timing strobe of the codec and processor 8 as well as the codec clock signal are generated by the FIR chip 16 and synchronized with the time of the incoming receiving samples. The FIR chip 16 also generates control and timing signals for controlling the shape and timing of the bell voltage provided by the bell circuit 21. The monitoring timer module 38 provides a reset signal in case the processor chip 12 instructs does not perform properly.

The multi-loadable buffer 33 buffers a 3.2 MHz master clock signal received on line 23a of DIF chip 17, an advanced 3.2 MHz clock signal received on line 23b of DIF chip 17, and a reset signal which is received on line 51 from the monitoring timer 38. Unless otherwise indicated, all timing within the FIR chip 16 is derived from the 3.2 MHz clock signal on line 23a. The advanced 3.2 MHz clock signal on line 23b precedes the 3.2 MHz clock signal on line 23a with a cycle of a reference signal of 21.76 MHz contained within the DIF chip 17. The clock signal of 3.2 MHz is derived from the reference of 21.76 MHz in the DIF chip 17 and the minimum pulse width is therefore 276 nanoseconds. The forwarded 3.2 MHz clock signal from line 23b is provided from the buffer 33 via internal line 47 to the FIR transmit filter 42, and the codec timing module 44. The FIR transmit filter 42 is implemented, at least in part, by means of a ROM, which is pseudo-static and requires its activation input to be deactivated by the advanced 3.2 MHz clock signal on line 47 between successive accesses.

The HW reset signal on line 51 resets all internal circuits of the FIR chip 16 and provides a hardware reset to the modules of Figure 1.

The internal clock signals are either buffered versions of the master clock signal of 3.2 MHz received on line 23a or divisions of this clock signal.

The internal address decoding module 34 allows the processor chip 12 to access the internal functions of the FiR chip 16 to control these functions and determine their status. The internal address decoding module 34 receives processor addresses and processor strobe signals on bus 25. The internal address decoding module 34 provides output signals on internal bus 48.

The output signals on bus 48 of the internal address decoding module 34 include a read enable signal to the receive sample buffer 35, a control write signal as well as status read signals to the control and status registers 36, a write signal to the FIR transmit filter 42, slot and clock write signals to the receive timing module 39 a write signal to the transmit timing module 40 and control signal to the FIR transmit filter module 42 and the receive sample buffer 35, as well as an AM strobe signal that causes the receive timing module 39 to reset the slot timing. Only one of the respective read or write signals on bus 48 of the internal address decoding module 34 is active at a given time.

The receive sample buffer 35 receives four samples for each receive symbol time from the A / D converter 19 through line 27a at a rate of 64 kHz; buffers up to two data symbols, which is a total of eight samples; and then send these data samples to the processor chip 12 through the processor bus 25. The receive sample buffer 35 is implemented by means of a dual-page RAM. The receive sample buffer 25 receives a read enable signal on internal bus 48 from the internal address decoding module 34 and a write strobe signal on internal line 49 from the receive timing module 39.

The control and status registers 36 allow the processor chip 12 to control the internal function of the FIR chip 16, and allow the processor chip 12 to read the status of the FIR transmit filter 42 and the receive sample buffer 35, as well as other internal signals. The control signals are provided by the processor chip 12 through the processor bus 25 and the status indicia are derived from various internal modules of the FIR chip 16. The status indicia are provided to the processor chip 12 via the processor bus 25. The status indications are received underload, received overload, transmit underload, transmit overload, start-of-frarae, slot start reception, transmit symbol clock signal, receive symbol clock signal, and FIR transmit filter capacitance exceeded.

The control signals, which are provided by the control registers 36 to the internal circuits via the internal bus 48, include the following: transmit enable signal, modulation level, call enable signal, software reset signal, three state signal, and monitor strobe signal.

The transmit enable signal indicates the start of a transmit slot based on the transmit delay determined in the transmit timing module 40.

The modulation level signal is provided to the receive timing module 39 and determines whether a slot length is 180 or 360 symbols.

The software reset signal allows the processor chip 12 to reset internal functions within the FlR chip 16.

The three-state signal allows the processor chip 12 to disable the outputs of the FIR chip 16.

The bell activation signal allows the processor chip 12 to turn the bell circuit 21 on and off. This signal provides a cadence of two seconds and four seconds to the ring signal.

The monitoring strobe signal allows the processor chip 12 to reset the monitoring timing module to prevent the occurrence of a hardware reset.

The processor chip 12 receives a receive clock interrupt (RXCLKINT) signal from the receive timing module 39 via line 26c when data is written into the first four locations of the dual-page RAM of the receive sample buffer 35. The processor chip 12 then reads the receive samples from the first four locations of the dual-page RAM via processor bus 25. At this time, samples are written in the following four locations of the dual-page RAM at a rate of 64 kHz. The 16 kHz event is a derivative of the 64 kHz event, which keeps the read and write events in sync. This ensures that read and write operations do not occur simultaneously at any memory location and also ensures adequate response time of the processor chip 12.

A transmit symbol buffer in the FIR transmit filter 42 receives transmit symbols from the processor chip 12 through the processor bus 25 and buffers up to two transmit symbols. The processor chip 12 receives an interrupt every other transmit symbol time to write two more symbols into the transmit symbol buffer.

The transmit symbol buffer in the FlR transmit filter 42 receives a write signal via the internal bus 48 of the internal address decoding module 34.

After each transmit clock signal interrupt (TXCLKINT) at 8 kHz on line 26a, processor chip 12 writes two 5-bit transmit symbols. The data has a DPSK gray-code format. The transmit symbol buffer produces a symbol every 16 kHz for processing by the FlR transmit filter 42. This data is double buffered due to an asynchrony between the FIR chip 16 and the processor chip 12. The last data value is repeated until new data is written. Zero data can be repeated in this way. The transmit symbol buffer is cleared during a reset.

During a workout, a fixed sequence of symbols is sent to the FIR chip 16 by the processor chip 12. The FIR chip 16 performs FlR filtering on these symbols and sends 1,4 pairs to the DIF chip 17.

The radio 20 loops the data back to the A / D converter 19. The samples are read by the processor chip 12 as during the on-line mode and the coefficients of the processor receive filter implemented in the processor chip 12, be adjusted. The only timing critical in the training is generated by the receive and transmit timing modules 39, 40.

The receive timing module 39 generates all reference clock and strobe signals for processing the receive symbols. The timing is adjusted by the processor chip 12 in such a way that the processing can be synchronized with the receive samples received via line 27a of the base station. The receive timing module 39 includes a fractional receive clock timing circuit and a receive slot timing circuit. The purpose of these two circuits is to synchronize the receive timing of the modem within the processor chip 12 with the receive samples received on line 27a of the base station, and through the A / D converter 19, and also regulate the transmit timing module 40 and the codec timing module 44.

The receive timing module 39 receives clock control at a rate of 3.2 MHz and receives the following control signals from the processor chip 12 through the processor bus 25: an AM strobe signal, a receive slot clock write signal, and a receive bit tracking signal.

Several output signals are generated by the receive time control module 39. A 64 kHz write strobe is provided on line 49 to control write to the receive sample buffer. A 64 kHz A / DSYNC strobe signal is provided on line 27b to the a / d converter 19 to synchronize its operation. Also, an 8 kHz strobe signal is provided to the codec timing module 44 through line 52. A 16 kHz receive clock interrupt signal (RXCLKINT) on line 26c and a start receive clock interrupt signal (RXSOSINT) on line 26b are supplied to the processor chip 12. A receive slot forward timing strobe is provided on line 54 to control the transmit timing module 40.

The fractional timing circuit in the receive timing module 39 is set by the processor chip 12 to generate the start receive slot interrupt signal on line 26b. The processor chip 12 determines the location of an AM (strobe signal) hole transmitted by the base station during acquisition. When the processor chip 12 detects the AM strobe signal, the slot timing control in the receive timing module 39 is reset by a reset signal from the processor chip 12. This synchronizes the frame and the slot marker signals with the AM strobe signal. The frame marker signal is a 62.5 με pulse that occurs every 45 milliseconds.

The incoming receive symbols are demodulated by the processor chip 12 and the timing is further adjusted if necessary. To adjust the 16 kHz receive symbol clock, the processor chip forces the fractional timing (bit follow) circuit to shorten or lengthen the 64 kHz strobe signal by up to fifty 3.2 MHz periods.

The processor chip 12 monitors the relationship of the receive symbols with the frame timing and performs adjustments of the 16 kHz receive clock signal accordingly. When the receive clock is adjusted, the slot and frame mark signals are also changed because they are a derivative of the receive clock signal. In order to keep the number of pulse code modulated (PCM) samples going to and from the SLIC and the codec circuit 11 synchronized with the frame timing, the receive timing module 39 controls the coding timing module 44.

The transmit control module 40 includes a transmit delay circuit and a transmit control timing circuit. These circuits generate a transmit clock interrupt signal (TXCLKINT) which is supplied to processor chip 12 via line 26a. The transmit timing module 40 is synchronized with the receive timing module 39 by the receive slot pre-timing strobe, which is provided to the transmit timing module by the receive timing module 39 on line 54 and is used to reset the transmit delay circuit, which in turn generates the transmit slot marker signal. The timing of the transmitter clock signal is based on the internal clock signal of 3.2 MHz.

The processor chip 12 also controls the transmit delay as well as the transmit timing circuitry by providing a transmit data write control signal through the processor bus 25.

The transmit control module 40 provides a transmit / receive control signal on line 30 to the radio 20. This signal determines whether the radio is transmitting or receiving data.

The transmit timing module 40 also controls the transmit symbol shift, ROM addressing, accumulation timing, and I, Q product storage for supply to the DIF chip 17.

The transmit timing module 40 provides control signals on line 56 to keep the FIR transmit filter 42 synchronized with the transmit symbol and slot timing. This synchronization is accomplished in accordance with the transmission slot timing marker signal. After a reset, the transmit timing module 40 actively produces control signals on line 56 as soon as a transmit slot begins.

The FIR transmit filter module 42 includes a ROM, which implements an FIR filter by providing I and Q data products in response to addressing the ROM for lookup, through a combination of transmit symbols received from the processor chip 12 via the processor bus 25 as well as SINUS and COSINUS coefficient counts provided by a counter within the FIR transmit filter module 42. The FIR transmit filter 42 accumulates six sequential I and Q data products and stores results for output to the DIF chip 17 via line 24a.

The minimum frequency required for operation of the FIR transmit filter 42 is determined by the symbol rate (26 kHz) multiplied by the number of I and Q samples (2) multiplied by the number of coefficients (10) multiplied by the number of taps (6) = 1.92 MHz. The 3.2 MHz main clock signal meets this minimum frequency requirement. Hair periods are added to compensate for the faster run time.

The transmission time control module 40 is controlled at a clock rate of 3.2 MHz, which defines a cycle period. Because this clock rate is greater than the required minimum of 1.92 MHz, the FlR transmit filter 42 generates signals for the first six of the ten cycle periods.

Each new transmit symbol must be loaded into a circulating buffer in the FlR transmit filter 42 at the rate of 16 kHz. The new transmit symbol and the previous five transmit symbols are stored in the circular buffer. The oldest transmission symbol is deleted when a new transmission symbol is added. The FIR transmit filter 42 has an output rate of 320 kHz. Ten I data values and ten Q data values are generated from each transmission symbol. Table 1 (see below) shows how I and Q as well as zero information can be derived from each 5-bit value.

The data in the circulating buffer is rotated at 6 out of every 10 cycles. A new transmit symbol and the five previous transmit symbols reside in the circulating buffer for twenty of these ten cycle periods. The coefficient portion of the ROM address is also increased at six of the ten cycle periods. An accumulator in the FIR transmit filter 42 adds the results of each I data product provided by the ROM for each of the six cycle periods. Therefore, the accumulator register is cleared for the first addition, and each successive addition is clocked into a feedback register of the accumulator so that it can be added to the recently requested product. Once six additions have been made, the result is fed to an output shift register under clock control. The same process occurs for the same coefficients and the Q data products provided from the ROM for each transmit symbol.

The ROM address lines allow to look up sixty COS coefficients and sixty SIN coefficients for four possible I, Q data indexes. This requires seven address lines for coefficients and two address lines for I, Q data. The output of the FIR filter requires 10 bits.

Two additional bits are required to maintain the accuracy of the fractional part of the looked-up value. This results in a ROM size of 512 x 12. The MSB of the I, Q data index is passed around the ROM to a 1's complement circuit which forces the output of the ROM to be inverted or not inverted .

If the symbol addressing the ROM is a zero symbol, the zero bit controls four of the seven coefficient address lines. Since seven address lines are used to look up the coefficient, this provides 12Θ locations. Only 120 coefficients are needed. Therefore, eight unused locations are left. Zero values are stored in these locations so that zero information can be easily output from the ROM.

A 2's complement function is implemented using a 1's complement and passing a logic 1 to the next adder. The output of the adder is fed back to the input of the adder for successive additions or output through a multiplexer to an output shift register. The output is rounded using only the ten higher bits.

The outputs of the circulating buffer of the FIR transmit filter are set to zero after a reset. This allows zero information to be processed until new transmit symbol values are loaded. Ι data is first processed followed by Q data.

The transmit clock interrupt signal only occurs during a transmit slot. The processor does not know when a transmission slot starts or ends except by responding to this interrupt. The signal has an active duration at logic zero of a 3.2 MHz clock period to ensure that the interrupt is not active once it has been processed. The radio clock interrupt occurs every other symbol time (16 kHz / 2).

The receive clock occurs during a full frame. The pro.ces sor chip 12 masks this interrupt by using the receive slot marker signal as a mask. The receive clock interrupt has an active duration at logic zero of a 3.2 MHz clock signal.

The transmit slot start interrupt occurs every 11.25 milliseconds, and has an active duration at logic zero of a period of the 3.2 MHz clock signal.

Each interrupt signal is forced to take an idle state of logic "1" when resetting.

The codec timing module 44 generates timing strobes and sends the necessary clock signal via lines 29 to the SLIC and the codec circuit 11 to have eight data bits transferred between the codec and the processor at a rate of 8 kHz. The codex 11 receives and sends 8 data bits every 8 kHz. The codec timing module 44 sends a codec clock signal over line 29a and a codec sync signal over line 29b. The code clock signal on line 29a is generated at a rate of 1.6 MHz by dividing the forwarded clock signal of 3.2 MHz by two. A 6 kHz pulse of a 3.2 MHz period is received from the receive timing circuit 39 and is re-clocked to occur for a period of 1.6 MHz to ensure that it occurs with respect to the rising edges of the clock signal of 1.6 MHz. With these two signals, transfer of the PCM data between codec 11 and the processor chip 12 is realized. This allows the subscriber PCM data to be synchronized with the base station PCM data.

The bell control module 45 responds to a bell enable control signal from the processor chip 12 and is provided from the control and status register 36 on internal bus 48 by generating a 20 Hz square wave signal on line 31 as well as two phase control signals of 80 kHz, PHASEA on line 31b and PHASEB on line 31c and transmitting these signals to the bell circuit 21. The square wave 20 Hz signal on line 31a controls the polarity of the ring voltage supplied by the bell circuit 21 to the telephone. phone interface circuit 10. The 80 kHz phase signals on lines 31b and 31c control the pulse width modulated power source in the bell circuit 21. A reset or a SLIC bell command signal on line 29c of the SLIC portion of the SLIC and codec circuit 11 turns these signals off or be ignored on lines 31a, 31b and 31c after the ringer enable signal from the processor chip 12 has turned it on. This ensures that the ringer is disabled if a reset occurs or the telephone handset is lifted.

Since the bell circuit 21 generates a high voltage and dissipates a lot of power, this voltage is not generated unless the processor chip 12 requests it.

The external address decoding module 37 generates chip select signals on the processor bus 25 which are used by the processor chip 12 to access the DIF chip 17. The UART hardware, and the slow memory EPROMs 14 in separate distinct address segments. The processor chip 12 provides eight MSB address lines, data space and program space signals. These are decoded to generate the appropriate chip select signals.

The monitor timer 3Θ generates a 50 millisecond hardware reset pulse on line 51, which resets all modules on FIR chip 16 and all subscriber unit modules in Figure 1. The monitor timer 38 generates a pulse if not reset within a 512 millisecond period by the monitoring strobe signal provided on bus 48 by the control and status registers 36.

The DIF chip 17 is coupled to the processor chip 12 through the processor bus 25, to the FIR chip 16 through lines 23 and 24, to the DAC 18 through line 71, and to an oscillator in the radio 20 through line 72.

The oscillator in the radio 20 provides a main clock signal of 21.76 MHz on line 71 to the DIF chip 17.

Referring to Figure 3, the DIF chip 17 includes a clock generator 60, a processor decoding module 61, an FIR chip interface module 62, an interpolator 63, a control register 64, tuning registers 65, a DDS phase accumulator 66, a DDS SIN and COS generator module 67, and a noise shaper 69. In combination, the DDS phase accumulator 66 and the DDS SIN, COS generator f7 form a direct digital synthesizer (DDS) for digital synthesis generation of a digital intermediate frequency signal.

The DIF chip 17 is an ASIC chip, which is arranged as a processor data memory.

The DIF chip 17 operates in one of two modes of operation, a mode in which a modulated carrier is generated, and a pure carrier mode. In the mode where a modulated carrier is generated, baseband data is input into the I, Q domain and this data is used to modulate the pure carrier generated by the DDS function of the DIF chip 17. in the mode where the pure carrier is generated, the baseband data inputs are ignored and an unmodulated carrier of the DDS is provided to the DAC 18.

The clock generator 60 generates all timing signals and clock signals within the DIF chip 17 and also generates the 3.2 MHz clock signal as well as the advanced 3.2 MHz clock signal which are applied to the FIR chip 16 on lines 23a and 23b. The two primary timing signals used within the DlF chip 17 are a clock signal of 21.76 MHz and an interpolation gate signal of 2.56 MHz. The 3.2 MHz clock signal is used internally to shift I and Q data on line 24a from the FIR chip 16 to the FIR interface module 62.

The clock generator 60 buffers the 21.76 MHz clock signal received on line 72 of the oscillator in radio 20 and provides a buffered 21.76 MHz clock signal on line 71a. This buffering is performed to provide sufficient driving capability for internal functions and to minimize distortion of the clock signal. The buffered 21.76 Mhz clock signal also provides a clock signal for the DAC 18 and other external circuits.

The clock generator 60 provides the 3.2 Mhz clock signal by dividing the 21.76 MHz clock signal by 6 and by 8 according to the following sequence: 6-8-6-8-6, thus resulting in an average dividing factor of 6 1.8 (21.6: 6.8 = 3.2). The effect of this variation per period is a minimum period of 276 nanoseconds and a maximum period of 368 nanoseconds. A forwarded version of the 3.2 MHz clock signal is also generated as the forwarded 3.2 MHz clock signal on line 23b. Both clock signals are identical, except that the ROM deselect signal on line 23b is ahead of the 3.2 MHz clock signal on line 23a with a clock cycle of 21.76 MHz.

The clock generator 60 provides the 2.56 MHz gate signal on internal line 74 by dividing the 21.76 MHz clock signal by 8 and by 9 in an equal sequence (8-9-8-9 -...), which therefore results in an average division factor of 8.5 (21.76: 8.5 * 2.56 MHz). This signal is used by interpolator 63 and modulator 68.

The processor decoding module 61 allows the processor to control all internal functions of the DlF chip 17. The processor decoding module 61 decodes processor addresses and processor strobe signals received from data space on the processor bus 25 to provide internal write strobe signals, which are provided on internal bus 76 to the control register 64 and the tuning registers 65 to enable the processor chip 12 write control and configuration data. Only one output from the processor decoding module 61 is active at a given time. The processor addresses determine which output signal is generated. If a function within the address space of the DIF chip 17 is selected, a chip select signal on line 24c of the FIR chip 16 becomes active.

The FIR interface module 62 receives the I and Q samples from the FIR chip 16 on line 24a in a serial format and converts them to a 10-bit parallel format in which they are provided to the interpolator module on line 77. Q gate signal on line 24b of the FIR chip 16 is used to distinguish the I data from the β data. The FiR interface module 62 also subtracts previous I and Q samples from actual samples to form ΔΙ and AQ samples which are then shifted four places to the right {: 16) to form the correct increment for the interpolator module on line 78. Since the FIR interface module 62 provides data to the interpolator 63, a synchronization signal is sent by the FIR interface module 62 to the clock generator 60 to synchronize the 2.56 MHz gate pulse provided on line 74.

Interpolator 63 accumulates the AI, AQ at a rate of 160 kHz x 16 = 2.56 MHz and provides interpolated I and Q samples to modulator 68 on lines 80 and 81, respectively. Interpolator 63 performs x16 linear interpolation to reduce of 160 kHz sampling rights contained in the baseband data received from the FIR chip 16.

Interpolator 63 successively accumulates the Al and AQ samples to generate an output at a rate of 2.56 MHz. At the end of an accumulation cycle (16 repetitions), the interpolator output should be equal to the flow of I and Q samples. This is critical because the next accumulation cycle begins its cycle with the current data. In order to ensure that the data is correct, during the last accumulation cycle, the current I and Q data are input directly into the output registers of the interpolator instead of the adder's output (which should contain the same data).

The control registers 64 are used to control and configure the DIF chip 17 and to select the operating modes. All control registers 64 are loaded by the processor chip via the processor bus 25.

There are three control registers 64. The first control register records a CW MODE signal, an AUTO TUNE H-L signal and an AUTO TUNE L-H signal. The second control register registers a SIGN SELECT signal, an OUTPUT CLOCK PHASE SELECT signal, an INTERPOLATOR ENABLE signal, a SERIAL PORT CLOCK SELECT signal, a SERIAL / PARAL-LEL MODE SELECT signal and a QUADRATURE ENABLE signal. The control functions associated with these signals are described later in the conclusion of the description of the other modules of the DlF chip 17.

The third control register activates and specifies the coefficients for the noise shaper 69.

There are three 8-bit tuning registers 65 for storing 24 bits of phase incrementation data for specifying the frequency of the DOS. This provides a 24-bit tuning word that allows a frequency resolution of (sampling frequency) / 224 = 21.76 MHz / 224-1.297 Hz. The DDS output frequency is equal to the resolution multiplied by the 24-bit tuning word.

The tuning registers 65 are loaded by the processor chip 12 through the processor bus 25. The tuning word is double buffered by the tuning registers 65 so that the processor chip 12 can freely write data to these registers without affecting the current DDS operation.

The tuning word is loaded from buffer tuning registers to output tuning registers every time a TUNE command is issued. The TUNE command is synchronized with the clock signal of 21.76 MHz to provide a synchronous transition.

The DDS phase accumulator 66 performs a modulo 224 accumulator of the phase increment provided on line 82 by the tuning registers 65. The output of phase accumulator 66 represents a digital phase value which is supplied on line 83. DDS SIN and COS generator 67. The DDS SIN and COS generator 67 generates a sinusoidal function. A DDS operates on the principle that a digitized waveform can be generated by accumulating phase changes at a higher rate.

The tuning word, which will be different at different subscon-no units, represents a phase change for the phase accumulator 66. The output of the accumulator 66 can be in a range from 0 to 224-1. This interval represents a phase change of 360 °. Although the accumulator 66 operates in the standard binary mode, this digitized phase display can be input into a waveform generator to generate an arbitrary waveform. In the DIF chip 17, the DDS SIN and COS generators 67 produce SIN and COS functions on lines 84 and 65, respectively.

The period of the waveform function is based on the time required to sum to the upper limit of the accumulator (224-1). This means that if a large phase incrementation is provided, this limit will be reached sooner. Conversely, if a small incrementation is given, a longer time will be required. The phase accumulator 66 performs a simple summing of the input phase incrementation and can be represented by the following equation:

where m is the number of repetitions, and φ1η (. simply represents the data applied to line 82 from the tuning registers 65.

In the embodiment of the DIF chip 17 described, the value of φτ is limited by the length of the accumulator to a maximum of 254. Therefore, the current phase can be described as:

Therefore, since the accumulator clock is designated as the input main clock signal of 21.76 MHz, a complete cycle contains 224 / φ1η <; at a period per repetition of 1 / 21.76 MHz. Therefore, the full cycle takes the following amount of time:

Because this period represents a 360® cycle, the reciprocal of this formula represents a frequency. The DDS frequency is therefore:

In the DDS SIN, COS generation module 67, the SIN and COS waveforms are generated so that complex mixing can be performed in the modulator. Each is generated by two look-up tables, which represent a rough and a fine estimate of the waveforms. The two values are added to form composite 12-bit 2's complement SIN and COS sign-output data on lines Θ4 and Θ5. The lookup tables are implemented in ROMs which are addressed by the fourteen most significant bits of the signal on line 63 of the DDS phase accumulator 66.

It is desirable to have as much phase and amplitude resolution as practicable. In the design of the DIF chip 17, a 14-bit phase input signal and a 12-bit amplitude data output signal are provided in the waveform generating section. If a pure processing power approach were to be taken to generate this data, very large tables would be required to generate all possible phase and amplitude values (e.g., 16K words x 12 bits each). In order to minimize the size of the table, the DIF chip 17 uses quadrant symmetry and trigonometric decomposition of the output data.

Because SIN and COS waveforms have quadrant symmetry, the two most significant bits of the phase data are used to mirror the single quadrant data about the X and Y axis. For the SIN function, the amplitude of the wave in the π to 2it interval has exactly the negative value of the amplitude in the 0 to π interval. For the COS function, the amplitude of the wave in the% / 2 to 3π / 2 interval is exactly the negative value of the amplitude in the 3it / 2 to n / 2 interval. Two MSB1 s of the phase accumulator specify the quadrant (00-1, 01-2, 10-3, 11-4). For the SIN function, the MSB of the phase data is used to negate the positive data generated for the first two quadrants. For the COS function, an XOR of the two phase data MSBs is used to negate the positive data generated for quadrants 1 and 4.

The above technique reduces the memory requirements by a factor of 4. This already results in a memory requirement of 4K words x 12 bits. In order to further reduce the table dimensions, trigonometric decomposition is performed at the corners. The following trigonometric identity is used:

By setting φ2 << φΊ the full approximation is as follows:

It is not necessary to use all bits of φ1 when calculating the second term of the equation so that it is a subset of φΊ.

The same approach can be used to generate the COS function because:

This results in a modification of the and $ j variables when calculating the COS function. The data stored in the COS RONs will include this angle modification so that no changes to the phase data are required.

The modulator 68 mixes the interpolated I and Q samples on lines 80 and 81 with the digital intermediate frequency signal represented by the complex SIN and COS function data on lines 84 and 85 to provide a modulated digital intermediate frequency signal on line 87.

The interpolated I, Q samples as well as the DDS output are digitally mixed by two 10 x 12 multipliers. The output signals from the mixing process are then summed by a 12 bit adder to form a modulated carrier. It is possible to change the operation of the modulator 68 by making all bits of the I input signal zero and making all bits of the Q input signal one. As a result, one multiplier will produce only zeros and the other will produce only the signal from the DDS SIN, COS generator 67. The sum of these two signals produces an unmodulated digital intermediate frequency signal.

Modulator 68 generates a modulated digital intermediate frequency signal on line 87 according to the following equation:

The 12-bit output from the DDS SIN and COS generator 67 is multiplied by the 10-bit interpolated I and Q samples from the interpolator 63 to generate two 12-bit products. The two products are then added (combined) to generate a 12-bit modulated output on line 87.

Since both the I multiplier and the Q multiplier generate 12-bit products, it is possible that a capacitance overrun could occur when their output signals are combined. It is therefore necessary to ensure that the size of the vector generated by I and Q never exceeds the value of one (assuming that 111, Q | are fraction numbers <. 1). If this is not guaranteed, a capacity overrun of the adder of the modulator is possible.

The noise shaper 69 provides a filtered modulated or unmodulated digital intermediate frequency signal on line 71b to the DAC 18. The noise shaper 69 is designed to achieve a reduction in the amount of noise power in the output spectrum caused by the amplitude quantization error.

The operation of the noise filter 69 is based on the fact that the quantization noise is a normally random process, and that the spectral density of the power of the process has a smooth variation over the frequency band. The desired output signal is superimposed on this quantization noise floor. The noise generator is a simple multi-branch filter with finite impulse response (FIR). The filter creates a zero which reduces the power of the quantization noise in a certain portion of the frequency band. When the desired signal is superimposed on the filtered noise spectrum, the effective SQNR increases.

The transfer function of the FIR filter is given by

£ .eu trdp wej.Ke u ^ btdai uu two optexxexs ue ^ u a new external value of b in the range +1.75 to -1.75 (in binary weights of 0.25, 0.50 , 1.0) which will move the zero of the filter over the output frequency band so that it can be placed as close as possible to the desired output frequency in order to obtain maximum SQNR performance.

The zero frequency can be calculated by solving for the roots of the above equation in the z-plane. The roots are a complex conjugate pair that lies on the unit circle. The zero frequency follows from the relationship: where Θ is the angle of the square root in the upper half-plane. The conjugate root will provide a zero mirrored around the Nyquist frequency.

Table 2 provides a list of zero frequencies generated by the binary weighted second tap. Suppose that b3, b2 and b1 correspond to the weights 1.0, 0.5, 0.25, that a 'V' symbol means that the branch is equal to its weight, that a '-' symbol means that the tap is equal to the negative value of its weight, and that “0” means that the tap has no weight. Some of the zero frequencies are the same as in other combinations simply because the possible combinations sometimes overlap (eg 1.0 + 0.5 - 0.25 = 1.0 + 0.0 + 0.25). Is 1.00.

All timing is derived from the 21.76 MHz knock signal on line 71a.

The functions associated with the signals in the control registers 64 are now described.

When the CW MODE signal is set, the I input signal supplied to the respective multiplier in the modulator 68 all bits are made zero, and the corresponding Q input signal all bits are made one. The result is that an unmodulated carrier wave will be generated. This function is double buffered and the loaded data will not become active until a TUNE gestation is provided.

The INTERPOLATOR ENABLE signal activates the x16 interpolator on the I, Q samples. If the INTERPOLATOR ENABLE signal is not set, the I, Q data is fed directly to the multiplier.

External memory required for the operation of the processor chip 12 is provided by a fast memory 13 and a slow memory 14. Access to the fast memory 13 is obtained by means of an address decoder 15. The fast memory 13 is a cache memory implemented in a RAM that has zero wait cycles. The slow memory 14 is a bulk memory implemented in an EPROM, which has two wait cycles. The slow memory 14 is coupled to the processor chip 12 to store processing codes used by the processor chip 12 when the codes need not be operated with zero wait cycles; and the fast memory is coupled to the processor chip 12 to temporarily store processing codes used by the processor chip 12 when the codes are operated with zero wait cycles. When procedures are to be completed with zero waiting cycles, the code can be transferred from slow memory 14 to fast memory 15 and activated there. Such procedures include interrupt service routines, symbol demodulation, RCC acquisition, BPSK demodulation as well as voice and data processing.

The processor chip 12 includes a single digital signal processor of the model TMS320C25, which performs four main tasks, a subscriber control task (SCT) 91, a channel control task (CCT) 92, a signal processing task (SPT) 93, and a mode processing task (MPT) 94 as shown in Figure 4. These four tasks are controlled by a supervising module 95. The SCT serves the telephone interface and high-level call processing. The CCT controls the model and RELP operation as well as timing, and makes power level and transmit timing adjustments as requested by the base station. The SPT performs the RELP, echo cancellation, and tone generation functions. The supervisory organ calls these four tasks sequentially and communicates with them by means of control words.

The SCT 91 provides the high-level control function within the subscriber unit and has three basic operating modes: idle state, voice mode and termination.

After switching on the supply voltage, the SCT enters idle mode and remains in that state until an actual speech connection is made. While in idle mode, the SCT monitors the subscriber telephone interface for activity and responds to base station requests received through the radio control channel (RCC).

The primary function of the SCT is to guide the subscriber unit by building and terminating voice connections on the radio channel. However, before the unit can establish a call of any kind, it must find the correct base station. The SCT determines which RCC frequency to use and sends the frequency information to the CCT. A description of the initialization of a communication channel between the subscriber unit and the base station is given in U.S. patent application no. 07 / 070,970, filed July 8, 1987.

Once the subscriber unit has obtained RCC synchronization, it can establish a call by exchanging messages via the RCC with the base station, and by monitoring and setting hardware signals on the telephone interface. The following overview briefly describes the events that occur during call setup.

Normal call building to initiate a call begins with the subscriber picking up the handset to initiate a service request. The SCT sends a CALL REQUEST message to the base station. The SCT receives a CALL CONNECT message. The SET gives the CCT a signal to attempt to synchronize the assigned voice channel via the CALL CONNECT message. The CCT establishes synchronization on the voice channel. The subscriber receives a dial tone from the exchange. Connection setup is complete. The exchange also provides the support needed to terminate the call.

Normal call setup for call termination occurs as follows: the SCT receives a PAGE message from the base station. The SCT replies with a CALL ACCEPT. The SCT receives a CALL CONNECT message. The SCT sends a signal to the CCT to attempt to establish synchronization on the assigned voice channel via the CALL CONNECT message. The CCT establishes synchronization on the voice channel. The SCT starts the bell generator to apply a bell signal to the local loop. The subscriber picks up the handset, the call is stopped. The voice connection is complete.

The SCT implements the call building and termination operations as a finite state machine.

If a voice channel assignment is successfully completed, the SCT switches to the speech mode and performs a very limited range of support functions. Loading of the SCT = processor is minimized at this time to ensure maximum availability of processor capacity for the algorithms of RELP speech compression, echo cancellation and modem processing.

The SCT enters Abort mode as a result of an unsuccessful call set-up attempt or an unexpected sequence of call terminations. During the abort mode, a repeat call is sent to the telephone receiver. The SCT monitors the subscriber telephone interface for an interrupt signal (handset on-hook for an extended period of time) at which time the subscriber unit enters idle mode. Base station requests received through the radio control channel (RCC) are rejected until hang-up is detected.

The CCT 92 functions as a link level channel controller in the baseband software. The CCT has three basic states: RCC operation, refinement and voice operation.

When turned on, the CCT enters the RCC operating state to search for and then support the RCC channel.

The RCC company includes the following functions: AM hole control; monitoring the synchronization and status of the modem task; timing correction of the radio channel; RCC message filtering on receipt; RCC message formatting when transmitting; I / O monitoring of the PCM buffer; as well as link information processing.

After a voice connection is established, the CCT enters the refinement state to fine tune the fractional timing of the modem. Refinement includes the following functions: interpreting and responding to refinement bursts; creating and formatting refinement bursts when transmitting; sending messages to the SCT as appropriate; monitoring the modem status; and X / 0 monitoring of the PCM buffer.

After the refinement has taken place, the CCT starts the speech operation, which includes the following functions: support of code word signaling; repairing dropouts; monitoring synchronization and modem status; and 1/0 monitoring of the PCM buffer.

The CCT 92 has three basic operating modes: rest, refinement and voice operation. The following is an overview of the state transitions that occur in CCT operation.

After a reset, the CCT goes to rest and remains inactive until it receives channel assignment instructions from the SCT. The SCT provides the CCT with a frequency to search for the radio control channel (RCC). The CCT then instructs the MPT to synchronize the receiver to the appropriate frequency and search for an AM gap. If an AM gap is not detected within a predetermined period of time, this will result in the CCT applying to the SCT for a different frequency to be searched. This continues indefinitely until the AM hole detection is successful.

After an AM gap has been successfully detected, the CCT begins to check if the unique word is present in the received data. A small window around the nominal position of the unique word is scanned because the AM hole detection process may have a deviation of a few symbol durations. Once the unique word is located and the CRC error detection word is verified to be correct, the exact receive symbol timing can be determined. The TDM frame markers are then corrected to have the correct setting and then normal RCC support begins. If the unique word cannot be located, the AM hole detection is considered false and the CCT requests the SCT for a new frequency assignment.

During RCC operation, the CCT filters received RCC messages. The majority of base station RCC messages are zero patterns and are ignored after link information is read from the link byte. RCC messages containing actual information are forwarded to the SCT for processing. If the RCC synchronization is lost, the CCT requests the SCT for a new frequency. The SCT will respond with the correct frequency in accordance with the RCC frequency search algorithm.

When the SCT initiates a voice call, the CCT is assigned a voice channel and a time slot. The CCT makes the subscriber unit active in accordance with this assignment and begins the refinement process. During refinement, the base station and subscriber units transmit a BPSK signal specifically designed to assist the modem in fractional bit-time acquisition. The base station CCU sends the bit timing offset back to the subscriber unit as a two's complement correction value. The CCT maintains a time average of this feedback offset. Once the CCT determines that the fractional timing value is within a required tolerance, it corrects the subscriber unit transmit timing accordingly. The length of the time average is determined dynamically depending on the variation of the fractional time samples. After a timing correction, the time average is reset and the procedure is repeated.

Once the base station detects that the subscriber unit is within an acceptable timing tolerance, it terminates the refinement process and begins voice operation. The length of the refinement process is determined dynamically depending on the success of the subscriber unit timing corrections. Power and integer symbol timing are also monitored and corrected as necessary during the refinement process. If, over time, the subscriber has not found the base station refinement bursts, or if the refinement process cannot establish an acceptable timing, the connection is terminated and the CCT returns to RCC operation.

After the refinement is successfully completed, the CCT goes to voice mode at the assigned modulation level. The tasks of the voice company include controlling RELP and MPT operations, establishing voice synchronization and continuously monitoring the voice codewords transmitted from the base station. Local loop control changes, signaled via the codewords, are reported to the SCT as they occur. Incremental changes in power as well as fractional timing are also derived from the code words. Broadcast voice codewords are formulated by the CCT based on the local loop control provided by the SCT and the quality of the channel link as reported by the modem. The CCT returns to the RCC when the SCT performs a call termination sequence.

If the voice synchronization is lost, the CCT initiates a fading repair operation. After failing to reestablish a good voice connection after ten seconds, the CCT notifies the SCT of this condition, initiating a call termination. r; it returns the CCT to the quiescent state.

During a channel test operation, a speech burst is replaced with channel test data. Once a burst is received, it is analyzed for bit errors. The bit error count value is passed to the base station via bursts on the return channel.

The SPT 93 performs all digital signal processing (DSP) tasks within the subscriber unit. The various DSP functions are called as required, under the control of the supervising module 95.

The SPT includes a RELP module which is run from a very fast RAM. The RELP module performs RELP voice compression and expansion with echo cancellation. The RELP module transforms 180 byte blocks of 64 kbps PCM voice data to 42 bytes of compressed voice data using the RELP algorithm.

The SPT also includes a signal processing control module (SPC) that determines whether to generate tone generation or RELP. If RELP, the SPC determines whether to call the synthesis or analysis routine. The synthesis routine returns a parity error count value, which is processed by the SPTCTL routine. If tone generation is required, it determines whether the output signal should be silence or a repeat call.

The SPT is controlled through the assignments of the SCT and the CCT. These commands provide invocation and operation of the various functions within the SPT as required by the subscriber unit. For example, the RELP and echo cancellation software are only executed when the subscriber unit is active in a voice call. Call progress tones are generated at a time when the subscriber unit's handset is off-hook and RELP is not active. The tones include silence and a repeat call. With the exception of IDLE mode, the interrupt service routine that controls the PCM codec continuously functions as a foreground process, filling the circulating PCM buffer.

The control and modem functions are performed between analysis processing and synthesis.

The MPT 94 demodulation procedure is divided into two procedures: DEMODA and DEMODB, through which the RELP synthesis is allowed to be performed on the receive data in buffer A immediately after the DEMODA procedure is completed. After DEMODA, all internal RAM variables should be stored in external RAM, then reloaded in the internal RAM before DEMODB is executed. This is because RELP uses the internal RAM.

When the RXCLK interrupt on line 26e is received by the processor chip 12, the MPT reads four received receive data samples and then places them in a revolving buffer for processing by the demodulation procedure. Duit allows other tasks to be performed while receiving samples.

The MPT receives the RXCLK interrupt signal on line 26e from the FIR chip 16 every 62.5 ps during the receive slot. The RXCLK interrupt signal is masked by the hardware of the processor chip during idle or transmit slots.

The MPT receives the TXCLK interrupt signal on line 26 from the FIR chip 16 only during the transmit slot. The TXCLK interrupt signal informs the processor chip 12 when a new receive symbol is to be sent to the FIR chip.

The MPT reads four samples from the receive sample buffer 35 into the FIR chip 16 during each RXCLK interrupt on line 26e. The MPT resets the input and output address counters for the buffer at the beginning of the receive slot.

The MPT sends transmit symbols to the transmit symbol buffer 36 in the FIR chip 16.

The MPT supplies the data to the fractional timing circuit in the receive timing module 39 in the FIR chip 16 which is used to make the RXCLK interrupt signal on line 26e coincide with the base station transmission.

The MPT also synchronizes the DDS frequency with the transmission frequency of the base station.

Referring to Figure 5, the MPT includes the following modules: a supervising module 101, a training module 102, a frequency acquisition module 102, a bit synchronization module 104, a speech demodulation module 105, a symbol receive module 106, and a transmit module 107.

The supervising module 101 is the supervising body of the MPT task. It reads the MPT control word (CTRL0) from the RAM, and calls other routines according to the control word.

The training module 102 calculates a vector of 28 complex FIR filter coefficients and is activated in the rest mode after the power is turned on and approximately every three hours. A training transmitter implemented by the MPT is activated in a loop return mode to transmit a certain sequence of symbols. This sequence is looped back to a training receiver implemented by the MPT, in a normal mode, in advanced and delayed timing modes, and on higher and lower adjacent channels.

The training receiver uses the input waveform samples to generate a positive perfectly symmetrical matrix A of the order 28. Also, a 28 word vector V is generated from the input samples. The coefficient vector C follows from:

The B coefficient is then calculated according to the algorithm: b = λ-1 if λ is given.

The training transmitter is activated in loop-back mode to transmit five similar pairs of signal series. Every couple. consists of the following two signal series: X series: 9 zero symbols, "i", 22 zero symbols Q series: 9 zero symbols, "j", 22 zero symbols

The "i" can be any symbol. The "j" is a symbol different from "i" with 90®.

The receiver's processing tasks are to set the AGC so that the signal peak in normal mode is 50 to 70% of the maximum. The AGC is increased by 23 db for the fourth and fifth modes.

Reading and saving the input samples. The first 32 samples are discarded and the next 64 samples are stored in each series.

Build up matrix A (28, 28). The following process is performed in normal mode:

The addition applies to any N that meets:

For the advanced and delayed series, the same process is performed with the difference that the term resulting from N = 8 is not added. In the channel series of the upper and lower adjacent channels, the following process is performed:

The addition applies to any N that meets:

Creating the vector V (1:28) from the samples of the first pair of sequences:

Re {V (I)} = X (32-I); where X are samples from the first (I) series.

1m {V (I)} = X (32I); wherein X are samples of the second Q series.

Finding the coefficient vector C by solving the equation:

These processing steps are more fully described in U.S. Patent No. 4,644,561.

The frequency acquisition module 103 is used when the control channel is received to synchronize the receive frequency of the subscriber unit with the transmit frequency of the base station. This is done by correcting the DDS CW output signal until the energy in each of the two sidebands of the received signal is equal. Afterwards, the DDS transmit frequencies are corrected according to the calculated frequency deviation.

If the procedure fails to establish frequency synchronization, an appropriate error code is placed in the status word.

The bit synchronization module 104 is used when the RCC is received and after the completion of the frequency acquisition. A certain pattern is transmitted in the first 44 symbols in the RCC broadcast from the base station and it is used by the module to calculate the RXCLK deviation from the correct sampling time. This deviation is used to correct the RXCLK timing.

The speech demodulation module 105 is used to demodulate a speech slot. It is present in the slow EPROM and its functions are split between two procedures DEMODA and DEMODB.

The DEMODA functions include initializing parameters for the symbol receiving module 106; calling the symbol receiving module to process the received symbols for buffer A; and storing the variables in the external RAM before exciting.

The DEMODB functions include loading the variables from the external RAM to the internal RAM; calling the symbol receive module to process the received symbols for buffer B; and determining the link quality and other information after receiving all symbols in the slot.

The symbol receiving module 106 is transferred to the RAM when the CCT enters the speech mode. It is called by DEMODA or DEMODB to perform the following tasks: (1) reading I and Q samples from the circulating buffer; (2) FlR filtering of the I and Q samples; (3) determining the transmitted symbols and placing them in a buffer; (4) establishing a phase lock loop to synchronize the DDS with the incoming signal; (5) executing the bit tracking algorithm; (6) AGC calculation; and (7) accumulating data for the purpose of link quality calculation.

The transmitter module 107 includes the interrupt service routine for the TXCLK interrupt signal received on line 26e of the FIR chip 16, which occurs once every two symbols during a transmission slot. The functions of the transmit module 107 include: (1) extracting the transmit symbol from the RELP buffer; (2) performing inverse GRAY encoding thereon; (3) adding it to the previous broadcast phase (due to the EPSK transmission); and (4) transmitting it to the transmit buffer in the FlR chip 16.

The interface of the MPT with the baseband tasks is established via control and status words as well as data buffers in the shared memory. Procedures that require rapid execution are transferred to the cache memory when needed. These include the interrupt service routines, symbol demodulation, RCC acquisition and BPSK demodulation.

The MPT supervisor will not wait for RXSOS to read and decode the control word, but will do so immediately upon invocation.

The TMS320C25 enters a reduced power mode when the IDLE instruction is executed. In order to save electrical power, the equipment will be in rest mode most of the time when no phone call is in progress. Therefore, after a reset, the supervisor will acquire RCC synchronization and then go into idle mode until a predetermined interrupt causes a corresponding service routine to be performed. When operating in the reduced power mode, the TMS320C25 enters a sleep state and requires only a fraction of the power normally required to power the device. During the reduced power mode, the entire internal content of the processor is maintained to allow operation to continue unchanged when the reduced power mode is terminated. As soon as an interrupt is received, the processor chip 12 temporarily terminates the reduced power mode and resumes normal operation for a minimum duration of a main loop cycle. The requirements of the reduced power mode are checked at the end of the main loop each time to determine whether or not the subscriber unit should return to the reduced power mode. The slot clock signal is based on the slot timing generated by the hardware. When a slot marker signal pulls an interrupt, the routine increments the clock signal with a tap. Each tick of the clock represents a time of 11.25 milliseconds.

The receive and transmit functions of the UART are not interrupt-controlled, but are controlled by the background software (which controls the loading of the processor and prevents uncontrolled interrupt conditions). The processing code supports the XON / XOFF protθεοί for directly intercepting these characters and immediately activating or deactivating the UART transmission as appropriate. The speed of the receive and transmit operation is designed to be selectable by an external DlP switch device. The typical data reception rate is 9600 baud. A circulation buffer is used to control the transmission of the UART. The background software periodically checks the queue and initiates the transmission if it is not empty. It does this by sending bytes to the UART one byte at a time until the queue is empty.

The hook switch is sampled using the internal timing interrupt routine of the TMS320C25. In order to simulate DC signaling, a sampling period of 1.5 milliseconds is achieved. This interrupt is synchronized with the frame timing at the beginning of each frame; therefore, its frequency is phase locked to the base station to prevent undershoot or exceeding the capacity of the hook buffer. For each interrupt, a bit representing the hook detection signal (from the SLIC) is input into the 60-bit hook sample buffer (SSB). The SSB is examined by the SCT, in normal operation once every 45 ms. This interrupt is always activated by the software.

Claims (5)

Subscriber unit for processing communication signals in a wireless telecommunication system, the subscriber unit comprising means for transmitting the first communication signal, which transfers the information contained in a first information signal to a second unit within the system, and means for receiving a second communication signal from the second unit, which is processed by the subscriber unit to output a second information signal, the subscriber unit being able to communicate with the second unit over various high-frequency channels within a selected band of radio frequencies and wherein one of the channels is selected during communication between the subscriber unit and the second unit, and wherein the subscriber unit comprises: means for generating a high frequency base signal; means for generating a digital intermediate frequency signal such that the combination of the digital intermediate frequency signal with the high frequency basic signal produces a carrier signal having a frequency within the high frequency channel selected for communication, the first communication signal being produced based on both the high frequency basic signals as the digital intermediate frequency signal for transmission on the selected high frequency channel. Subscriber unit according to claim 1, characterized in that it comprises means (66) for storing phase enhancement data to produce digitized phase values and means (67) for generating the digital intermediate frequency signal based on the digitized phase values. Subscriber unit according to claim 2, characterized in that the means (67) for generating the digital intermediate frequency signal based on the digitized phase values function using predetermined values stored in a memory unit. Subscriber unit according to any one of claims 1 to 3, characterized in that it comprises means (12) for recoding the first information signal into digital input symbols; means (68) for modulating the digital intermediate frequency signal with the digital input symbols to produce a modulated digital intermediate frequency signal; means (68) for combining the modulated digital intermediate frequency signal with the high frequency base signal to provide the first communication signal; and means (67) using the digital intermediate frequency signal to demodulate the second communication signal received from the second unit. Subscriber unit according to claim 4, characterized in that it further comprises means for filtering the digital intermediate frequency signal through a noise shaping circuit (69) prior to demodulating the second communication signal received from the second unit.