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NL9100334A - Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een zelfregistrerend kobalt- of nikkel-silicide gevormd wordt. - Google Patents

Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een zelfregistrerend kobalt- of nikkel-silicide gevormd wordt. Download PDF

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Publication number
NL9100334A
NL9100334A NL9100334A NL9100334A NL9100334A NL 9100334 A NL9100334 A NL 9100334A NL 9100334 A NL9100334 A NL 9100334A NL 9100334 A NL9100334 A NL 9100334A NL 9100334 A NL9100334 A NL 9100334A
Authority
NL
Netherlands
Prior art keywords
layer
heat treatment
metal
silicon
silicide
Prior art date
Application number
NL9100334A
Other languages
English (en)
Dutch (nl)
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Priority to NL9100334A priority Critical patent/NL9100334A/nl
Priority to DE69215926T priority patent/DE69215926T2/de
Priority to EP92200459A priority patent/EP0501561B1/de
Priority to JP4069645A priority patent/JP2719863B2/ja
Priority to KR1019920002630A priority patent/KR100237095B1/ko
Publication of NL9100334A publication Critical patent/NL9100334A/nl
Priority to US08/038,045 priority patent/US5302552A/en

Links

Classifications

    • H10D64/011—
    • H10W20/069—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H10D64/0112—
    • H10W20/066—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/019—Contacts of silicides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/147—Silicides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/934—Sheet resistance, i.e. dopant parameters

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
NL9100334A 1991-02-26 1991-02-26 Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een zelfregistrerend kobalt- of nikkel-silicide gevormd wordt. NL9100334A (nl)

Priority Applications (6)

Application Number Priority Date Filing Date Title
NL9100334A NL9100334A (nl) 1991-02-26 1991-02-26 Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een zelfregistrerend kobalt- of nikkel-silicide gevormd wordt.
DE69215926T DE69215926T2 (de) 1991-02-26 1992-02-18 Verfahren zum Herstellen einer Halbleiteranordnung, wobei ein selbstregistrierendes Kobalt- oder Nickelsilizid gebildet wird
EP92200459A EP0501561B1 (de) 1991-02-26 1992-02-18 Verfahren zum Herstellen einer Halbleiteranordnung, wobei ein selbstregistrierendes Kobalt- oder Nickelsilizid gebildet wird
JP4069645A JP2719863B2 (ja) 1991-02-26 1992-02-19 半導体装置の製造方法
KR1019920002630A KR100237095B1 (ko) 1991-02-26 1992-02-21 반도체 소자의 제조방법
US08/038,045 US5302552A (en) 1991-02-26 1993-03-26 Method of manufacturing a semiconductor device whereby a self-aligned cobalt or nickel silicide is formed

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL9100334A NL9100334A (nl) 1991-02-26 1991-02-26 Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een zelfregistrerend kobalt- of nikkel-silicide gevormd wordt.
NL9100334 1992-02-26

Publications (1)

Publication Number Publication Date
NL9100334A true NL9100334A (nl) 1992-09-16

Family

ID=19858928

Family Applications (1)

Application Number Title Priority Date Filing Date
NL9100334A NL9100334A (nl) 1991-02-26 1991-02-26 Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een zelfregistrerend kobalt- of nikkel-silicide gevormd wordt.

Country Status (6)

Country Link
US (1) US5302552A (de)
EP (1) EP0501561B1 (de)
JP (1) JP2719863B2 (de)
KR (1) KR100237095B1 (de)
DE (1) DE69215926T2 (de)
NL (1) NL9100334A (de)

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US5506449A (en) * 1993-03-24 1996-04-09 Kawasaki Steel Corporation Interconnection structure for semiconductor integrated circuit and manufacture of the same
TW297142B (de) 1993-09-20 1997-02-01 Handotai Energy Kenkyusho Kk
JP2891092B2 (ja) * 1994-03-07 1999-05-17 日本電気株式会社 半導体装置の製造方法
US5624869A (en) * 1994-04-13 1997-04-29 International Business Machines Corporation Method of forming a film for a multilayer Semiconductor device for improving thermal stability of cobalt silicide using platinum or nitrogen
US5457069A (en) * 1994-08-31 1995-10-10 National Science Council Process for fabricating device having titanium-tungsten barrier layer and silicide layer contacted shallow junction simultaneously formed
US5895255A (en) * 1994-11-30 1999-04-20 Kabushiki Kaisha Toshiba Shallow trench isolation formation with deep trench cap
US5536676A (en) * 1995-04-03 1996-07-16 National Science Council Low temperature formation of silicided shallow junctions by ion implantation into thin silicon films
GB2339966B (en) * 1996-06-28 2000-12-20 Lg Electronics Inc Polysilicon thin film transistor
US5869396A (en) * 1996-07-15 1999-02-09 Chartered Semiconductor Manufacturing Ltd. Method for forming a polycide gate electrode
JP3003796B2 (ja) 1997-01-23 2000-01-31 日本電気株式会社 Ｍｏｓ型半導体装置の製造方法
US6127249A (en) 1997-02-20 2000-10-03 Micron Technology, Inc. Metal silicidation methods and methods for using same
US6156632A (en) 1997-08-15 2000-12-05 Micron Technology, Inc. Method of forming polycide structures
US6074960A (en) 1997-08-20 2000-06-13 Micron Technology, Inc. Method and composition for selectively etching against cobalt silicide
JP2008060594A (ja) * 1997-11-17 2008-03-13 Toshiba Corp 半導体装置の製造方法
US6071782A (en) 1998-02-13 2000-06-06 Sharp Laboratories Of America, Inc. Partial silicidation method to form shallow source/drain junctions
US6022801A (en) 1998-02-18 2000-02-08 International Business Machines Corporation Method for forming an atomically flat interface for a highly disordered metal-silicon barrier film
US6680248B2 (en) 1998-06-01 2004-01-20 United Microelectronics Corporation Method of forming dual damascene structure
TW383463B (en) 1998-06-01 2000-03-01 United Microelectronics Corp Manufacturing method for dual damascene structure
US6204177B1 (en) * 1998-11-04 2001-03-20 Advanced Micro Devices, Inc. Method of forming junction leakage free metal silicide in a semiconductor wafer by alloying refractory metal
KR100564416B1 (ko) * 1998-12-30 2006-07-06 주식회사 하이닉스반도체 반도체소자의 살리사이드층 형성방법
KR100628253B1 (ko) * 2000-08-09 2006-09-27 매그나칩 반도체 유한회사 반도체 소자의 자기 정렬 실리사이드 형성방법
US6890854B2 (en) 2000-11-29 2005-05-10 Chartered Semiconductor Manufacturing, Inc. Method and apparatus for performing nickel salicidation
US20020084502A1 (en) * 2000-12-29 2002-07-04 Jin Jang Carbon nanotip and fabricating method thereof
US6765269B2 (en) 2001-01-26 2004-07-20 Integrated Device Technology, Inc. Conformal surface silicide strap on spacer and method of making same
US6743721B2 (en) 2002-06-10 2004-06-01 United Microelectronics Corp. Method and system for making cobalt silicide
US6905560B2 (en) * 2002-12-31 2005-06-14 International Business Machines Corporation Retarding agglomeration of Ni monosilicide using Ni alloys
KR100947525B1 (ko) * 2003-03-12 2010-03-12 삼성전자주식회사 액정 표시 장치용 박막 트랜지스터 기판 및 이의 제조방법
KR100870176B1 (ko) 2003-06-27 2008-11-25 삼성전자주식회사 니켈 합금 샐리사이드 공정, 이를 사용하여 반도체소자를제조하는 방법, 그에 의해 형성된 니켈 합금 실리사이드막및 이를 사용하여 제조된 반도체소자
US6797614B1 (en) * 2003-05-19 2004-09-28 Advanced Micro Devices, Inc. Nickel alloy for SMOS process silicidation
KR20050111662A (ko) 2004-05-21 2005-11-28 삼성전자주식회사 압력 및 진동감지장치
US7575959B2 (en) * 2004-11-26 2009-08-18 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US7419907B2 (en) * 2005-07-01 2008-09-02 International Business Machines Corporation Eliminating metal-rich silicides using an amorphous Ni alloy silicide structure
US20070249149A1 (en) * 2006-04-21 2007-10-25 International Business Machines Corporation Improved thermal budget using nickel based silicides for enhanced semiconductor device performance
US20090258238A1 (en) * 2008-04-14 2009-10-15 Heraeus Inc. Silicide formation utilizing ni-doped cobalt deposition source
US8377556B2 (en) * 2008-11-26 2013-02-19 Stmicroelectronics Asia Pacific Pte., Ltd. Material for growth of carbon nanotubes
JP2009167530A (ja) * 2009-02-10 2009-07-30 Nippon Mining & Metals Co Ltd ニッケル合金スパッタリングターゲット及びニッケルシリサイド膜
US20110006409A1 (en) * 2009-07-13 2011-01-13 Gruenhagen Michael D Nickel-titanum contact layers in semiconductor devices
US20110031596A1 (en) * 2009-08-05 2011-02-10 Gruenhagen Mike D Nickel-titanum soldering layers in semiconductor devices
US9249497B2 (en) 2010-03-19 2016-02-02 Jx Nippon Mining & Metals Corporation Ni alloy sputtering target, Ni alloy thin film and Ni silicide film
CN102856177B (zh) * 2011-06-27 2015-01-28 中芯国际集成电路制造(北京)有限公司 半导体器件和用于制造半导体器件的方法
JP2023117618A (ja) * 2022-02-14 2023-08-24 東京エレクトロン株式会社 成膜方法及び成膜システム

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JPS567304B2 (de) * 1972-08-28 1981-02-17
US4912061A (en) * 1988-04-04 1990-03-27 Digital Equipment Corporation Method of forming a salicided self-aligned metal oxide semiconductor device using a disposable silicon nitride spacer
NL8801632A (nl) * 1988-06-27 1990-01-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij tijdens depositie van een metaal een metaalsilicide wordt gevormd.
US5047367A (en) * 1990-06-08 1991-09-10 Intel Corporation Process for formation of a self aligned titanium nitride/cobalt silicide bilayer

Also Published As

Publication number Publication date
EP0501561A1 (de) 1992-09-02
JP2719863B2 (ja) 1998-02-25
JPH0594966A (ja) 1993-04-16
DE69215926T2 (de) 1997-05-28
DE69215926D1 (de) 1997-01-30
US5302552A (en) 1994-04-12
KR100237095B1 (ko) 2000-01-15
EP0501561B1 (de) 1996-12-18
KR930018657A (ko) 1993-09-22

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BV The patent application has lapsed