NL8500526A - METHOD FOR ADDRESSING A MEMORY WITH A DELAY LINE WITH ANY ACCESSIBILITY AND SIGNAL PROCESSING DEVICE PROVIDED WITH SUCH A DELAY LINE. - Google Patents

Description

<PHN 11.296 1 N.V. Philips' Incandescent lamp factories in Eindhoven.

...... ".. Method for addressing a memory with random accessibility as a delay line and signal processing device provided with such a delay line.

The invention relates to a method for addressing. .....

a random access memory having an address length of n bits to function as a delay line with a delay length of L memory positions each accommodating one multi-bit data-5 element, which method recurents after predisposing an available memory area for any delay line contains the following steps: - addressing the memory area by means of a read pointer to read out a data element, 10 addressing the memory area on a data element by means of a write pointer at a predetermined distance relative to the read pointer - preparing an upcoming reading pointer by means of an incrementation.

Such a method is known from British published patent application 2 115 588, in particular figure 15. Four control data are required for the control of the memory, namely a running lées address, a running writing address, a start address and an end address. The running addresses were compared to the end address, and when this is reached, the starting address is entered as the new running address. In this way, several delay lines can be implemented simultaneously in a memory, for which four address quantities must then be stored. This therefore requires considerable administration. The present invention assumes that often different delay lines are addressed mutually synchronized, ie that the source data is presented in synchronization, or destination data is retrieved in synchronization. The data width (e.g. word width) for the different delay lines need not be the same. Moreover, it is not always necessary for the supply of the source data to proceed at the same speed, a simple ratio may also exist between these, for example as 1: 2. In all these cases synchronization can be easily obtained by dividing one “or several delay lines in parts, which serve as secondary

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PHN 11.296 2 delay lines are arranged in parallel, as it were. It is an object of the invention to accelerate the addressing of the memory, on the one hand at the level of the single memory cycle by bundling the largest possible number of basic memory operations 5 therein, and on the other hand at the level of read / write operations by limiting the address incrementation in number of bits, so that the data bus, which is usually narrower than the address bus, can also be used for transporting the addresses, while still requiring a relatively small number of address transport operations per memory operation, respectively advantage to also be obtained in case the width of the address bus is smaller than the width of the total address, for instance if the latter is built as a combination of row address and column address in the memory arrays.

The invention achieves the object because it is characterized in that for addressing several delay lines to be mutually synchronized to be addressed they are coupled in a series because the value of the write pointer for a previous delay line of the series is equal to the value of the read pointer for the next delay line of the sequence if present, that an address thus doubled is addressed in a read-edit-and-write operation, that the address step between two consecutive data elements of the same delay line has a value p greater than one, and modulo the length of the feed said multiple delay lines available contiguous memory area in which the data elements of the different delay lines are thus stored interchangeably in said memory area , and that the incrementation step 1 = (pxL) modulo the length of said area has a value which can be expressed in at least one recurrence period of the delay cycle for at least one delay line in a smaller number of address bits than is necessary to express the length of said memory area itself.

For example, for a memory capacity of 64k, 16 address bits are required. If the length of a delay line is, for example, 256 data elements, the described solution can in many cases suffice with an incrementation step that can be expressed in much less than 16 bits.

"It is advantageous if the value p with the length of said BAD <SffiS5ë $ S does not have a greater common sub-factor than 1.

PHN 11.296 '3

Thus, the relevant memory area can be traversed in full, successively, so that memory locations are skipped and the effective capacity is thereby reduced. or the organization with multiple partial memory areas would become complicated, respectively.

The invention also relates to a signal processing device provided with such a delay line: signal processing devices are widely used and it is often necessary to implement several mutually synchronized delay lines. In many cases, the present invention provides faster accessibility to memory, whereby either the machine cycle time of the signal processing device need not be extremely short, or there may be time left to perform other functions in addition to the delayed lines.

15 Brief description of the figures:

The invention is discussed in more detail with reference to a few figures.

Figure 1 shows a simple block diagram of a signal processing device according to the invention; Figures 2a-2c illustrate the operation of a delay line; Figures 3a-3h give first examples of a localization of the data elements in a memory; Figures 4a-4d give second examples of such localization; Figure 5 gives a further example of a memory organization with a delay line.

Brief description of a signal processing device;

Figure 1 shows a simple block diagram of a signal processing device according to the invention. In this basic arrangement, there is an arithmetic and logic unit 20, a read / write memory with random accessibility 22, and an input / output device for contacting the outside world 24. There is a control bus 28 which has several connections for exchanging control signals between the elements; this control bus is selectively connected to the extent necessary. Line 26 is the connection to the outside world. Line 30 is a database. There is no separate address bus to save bus lines. In an exemplary embodiment, the data bus has a width of 8 bits. Memory 22 has a capacity of 2 (64k) words

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8500526 PHN 11.296 '4 to 8 bits and therefore requires 16 address bits. To this end, an address processing unit is provided with an address register 34, an increirents register 32, and an address adder 36. Elements 34, 36 operate over a width of 16 bits, element 32 over 8 bits. The formed address can be returned from the adder 36 to register 34. Register 34 can be filled in twice from the data bus. If there is an incrementation. should be executed over a width greater than 8 bits, the incrementation is performed in two bus transport operations and the addressing operation is performed under a shift operation over the respective part of the incrementation quantity. The specific control terminals for the elements 32, 34, 36 are not shown for simplicity. Line 38 is the data line connection of memory 22.

In another embodiment, the data bus has a width of 12 bits, again smaller than the address length. Even if a separate address-15 bus is present, the solution to be discussed is advantageous in case an address quantity having the maximum possible length cannot be transferred in one bus transport. In the case of signal processing, successive quantities are often treated accordingly, for example because they represent digitized scanning values of a continuous signal such as an audio signal. This often requires different filter functions that are implemented with digital means. These filters often contain delay lines.

Figures 2a .. 2c illustrate the operation of a delay line. The line 39 indicates the address space, so that a memory area corresponds to a certain distance along this line. Three delay lines 40, 42, 44 have now been implemented. In this simple case, 40, 42 have the same numbers of data elements, 44 have 2x as many; the latter is possible in two ways: 30 a) the data data do not fit here in a single memory location so that they had to be divided over two memory locations: for each memory access to the delay lines 40, 42 two delay accesses must therefore be made in the delay line 44 b) Implement the delay aging time by this last delay line is twice as long (of course other ratios between the lengths also apply).

BAD ORIGINALHier is first of all considered case a). Working with read / write addresses, and with separate border addresses for all these PHN 11.296 '5. Delay lines are very complicated. Therefore, the conversion to Figure 2b is given first. Here, the delay lines are connected, where delay line 42 is given an address modification and changes to 46, while delay line 44 is split into extended ones. 5 traction lines 48, 50; delay line 48 for instance always receives the least significant parts of the data data, delay line 50 always receives the more significant parts. At the limit of two delay lines, there is now always a combination of a read operation and a write operation. Thereafter, an address modification takes place over L memory positions and the access is repeated. The occluded memory area may shift to the boundaries of the total memory space, respectively, to the boundary of a smaller, associated area.

If the upper limit is exceeded by an increment ation, the number indicating the length of the combined delay lines in address-15 positions is subtracted from them in a modulo operation. In this way, the marked area is always cycled through. A read change and write cycle takes less time than the sum of a read cycle and a write cycle. This accelerates operation.

The chosen design has the following imperfection: for each memory cycle, an address increment must take place, and this over a distance L. If the address length of the entire memory is n bits, the incrementation step may have an arbitrary value.

If this value is fixed, this is not such a drawback, but if different distances have been implemented, this information must always be supplied on the bus. If the length of the distance, expressed in bits, contains more bits than the bus width in bits, this requires two (or more) transport cycles, which slows down. Therefore, a different solution has been realized in Figure 2c. By mixing the different delay lines, a smaller distance as expressed in the number of physical memory locations is now achieved, as indicated by the small arrows. One incremental transport is now sufficient for each incrementation step. As will appear later, this cannot be achieved in all cases for all incrementation steps.

Figures 3a-3h give first examples of a localization of the data elements in a memory. In this simple example, the memory contains 16 address locations indicated by as many squares. There are two delay lines. The first contains the data

elements A1, B1, C1, ... G2 in this snapshot, so a total of seven BAD ORIGINAL

PHN 11.296 6 data elements. The second delay line similarly contains the seven elements Δ2 ... G2. The address step bags two consecutive data elements from these delay lines is p = 1. This is indicated by the connection arrow 100. The incrementation step between the read address of the first line (at A1) and the read address of the second line / write address of the first line (at A2 - there then comes H1) has a value of 7; this can therefore be expressed in three bits, which is 1 less than the total address width of 4 bits. The incrementation step between the read address of the second delay line and the write address 10 of this (so there comes H2) also has a value of 7. The further incrementation step back to the new read address of the first delay line then has a value of pxk, where k is the number of empty positions in the area plus 1; so here is k = 3. This step can be expressed in two bits, because the address is calculated 15 modulo the length of the mapped memory area. The two empty positions can be regarded as part of an empty delay line, thus having a length of L1 = k = 3. Thus, two incrementation steps must be supplied per cycle: alternating 7 (used twice) and 3.

If the address bus is 3 bits wide, it will take two transports, if the 20 bus is 2 bits wide, it will take three transports. If other memory recommendations are to be made between two response cycles for the delay lines, the current starting address must be transported once, and .1 incrementation step, of three bits. If the bus is three bits wide, it will take three transports, if the bus is two bits wide, it will even take four bus transports.

For the same two delay lines, Figure 3b gives a three position address step (arrow 102). The incrementation step, when all sixteen memory locations are available, is equal to 5: all address calculations now take place modulo 16. The incrementation step (arrow 104) can again be expressed in three bits. The incrementation step I can be calculated I = (pxL) mod G = (3x7) mod. 16 = 5.

L is the length of the delay line in number of data elements; G is the length of the memory area in memory locations.

The incrementation step for the dummy delay line is 3xk = 9, which can be expressed in four bits. The number of bus transports per. .cycle is now for the different bus widths:

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é PHN 11.296 7 with empty line without empty line 2. 4 4 3 3 3 "- (two equal incrementation steps need only be transported 5 times).

For the same two delay lines, Figure 3c gives an address step of five positions (arrow 106). The incrementation step (arrow 108) is now. three positions, this can be expressed in two bits.

I = (5x7) mod 16 = 3. For the dummy delay line, the incrementation 10 step is now equal to px3 = 15.

Figure 3d gives an address step of 7 positions (110), and the incrementation length is now one position (112); I = (7x7) mod 16 = 1. For the empty delay line the incrementation tap is now 7xp = 21 mod 16 = 5. Figure 3e gives an address step of 9 positions (114), and then 15 the incrementation step becomes fifteen positions, so this can only be expressed in four bits . For the dummy delay line, the incrementation step is equal to 11. Likewise, the further figures show successively, with further the incrementation step for the dummy delay line (I ') 20 3f: p = 11; I = 13; I '= 1.

3g: p = 13; I = 11; I '= 7 3h: p = 15; I = 9; I '= 13.

In these figures, in particular, figures 3b, 3c, 3d have a limited incrementation step for the "real" delay lines. For the "dummy" delay line, in particular Figures 3a, 3d, 3f have a limited incrementation step. Depending on the frequencies of the different incrementation steps, one solution or the other will give the best results. It turns out that the quantity p and the length of the memory area (here 16 locations) have no greater factor in common than "1". In that case, the delay lines run around the entire area. If the factor is larger, for example 2, this means that the memory locations fall into several classes: the delay lines are then limited to one class or the other.

This has no special advantages, but is usually no objection.

Correspondingly, Figures 4a ... 4d illustrate the implementation of two synchronous delay lines of unequal length. The lengths are indicated:

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The optimum value is always chosen for the address step; other address steps each give greater maximum incrementation length, the empty delay line not being considered. The invention can be applied in a corresponding manner if a memory region of a different length is predisposed or if several delay lines are to be provided. It appears that in most cases an advantageous value for the address step can be found to reduce the maximum incrementation length.

Figure 5 gives a further example of a memory-15 organization. There are three delay lines with the same lengths, each passing through one. block are indicated. In each delay line, a read operation takes place at the beginning and a write operation at the end, and a further read operation in the middle, so that a partial delay line is formed. In the figure the mixing of the delay lines by increasing the address step is not yet shown: reference is made to the other figures. Figures now indicate in which order the elementary memory perforations are performed. First read at "1". Then, at "2", a read change and write operation is performed. This is repeated at "3"; 25 is finally written at "4". Then the read operations at "5", "6", "7" are performed. For example, a further simplification can be performed because often similar operations (read, read / change / write) are performed as a series. Furthermore, the incrementation step between corresponding operations is often always the same (for example, between 5, 6, 7).

In the Figures 3, 4 the signed memory part can also always be completely filled with information elements. The invention also relates to a signal processing device with a signal device therein according to the above description. Either at the input, at the output or at both, a converter is required to convert an analog signal into a digital signal and / or vice versa.

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Claims (10)

1. A method of addressing a random access memory having an address length of n bits to function as a delay line with a delay length of L memory positions each accommodating one multi-bis data element, which method after predisposing an available memory area recurrently for any delay line comprises the following steps: - addressing the memory area by means of a read pointer to read out a data element, - means by means of a relative to the read pointer at a predetermined spaced write pointer addressing the memory area in order to write a data element, - preparing an next read pointer by incrementation, characterized in that for addressing a plurality of delay lines to be mutually synchronized to be addressed linked in a sequence because the value of the write pointer for a previous delay The line of the sequence is equal to the value of the read pointer for the next delay line of the sequence, if present, that a so-designated address is addressed in a read-change-and-write operation, the address step between two consecutive data elements of the same delay line have a value p greater than one, and modulo the length of the contiguous memory area available for said multiple delay lines is realized therein, that the data elements of the different delay lines are thus in said memory area are stored interchangeably, and that the incrementing step I = (pxL) modulo has the length of said area a value that is expressable in at least one delay cycle recurrence period for at least one delay line in a number of address bits smaller than 30 cm express the length of said memory area itself. Method according to claim 1, characterized in that the value p with the length of said memory area does not have a greater common division factor than 1. 3. Method according to claim 1 or 2, characterized in that for implementing a delay line for data data with a larger bit width than takes place at one memory address, the data data is split into data elements of a shorter length BAD One of the data data elements of the data data is delayed in one of a number> 1 of delay lines for those data elements. Method according to claim 1, 2 or 3, characterized in that in the case of at least two delay lines in a recurrence interval, each time must be read at a partial delay length, the last 5 read operations are performed after all write operations of the relevant recurrence period executed. Method according to any one of claims 1 to 4, characterized in that the delay length has at least two different values for different delay lines. 10. Method according to any one of claims 1 to 5, characterized in that in case the data elements stored together do not completely fill the predisposed memory area, an empty delay line in the series is coupled with a length that is one data element is greater than the unfilled part of the memory area. 7. Signal processing device. for stirring the method according to any one of claims 1 to 6, which comprises a processor element (20), a memory (22), connection means for the outside world (24), and a bus system for interconnecting said elements (28, 30), and wherein the memory includes address calculating means for forming a new current address from a current address and an incrementation step receivable over the bus system, characterized in that for addressing multiple mutually synchronously addressable together in a predisposed memory area contiguous stored delay lines which have at least one delay line writing address in common with a read address of a next delay line if present, in that the address step between two consecutive data elements of the same delay line has a value p> 1 and mödulo has the length for the aforementioned multiple delay available re 30 lines, contiguous memory area can be realized therein and the data elements of the different delay lines are thus stored interchangeably, said address calculation means are suitable for performing an address calculation with a modular with respect to the starting address of said memory area value, which is equal to the length of the area concerned, and which is used for at least one of said delay lines for at least one incrementation step * * transport tap across the bus system in that the incrementation distance I = (pxL) modulo the length of said area ^ f Λ ft P fl λ PHN 11.296 '11 * can be expressed in a smaller number of address bits than the length of said memory area itself can be expressed. 8. A signal processing device according to claim 7, characterized in that said bus system has a bus line shared by data and addresses. Signal processing device according to claim 8, characterized in that the bit width of said bus line is at least two bits smaller than the address length of said memory. Signal heating apparatus, comprising at least one signal-processing device according to any one of claims 7, 8, 9, characterized in that there are further provided a connection for communicating audio signals with the outside world and a converter for a conversion between analog and digital signals, the analog side of which is connected to the latter connection and the digital side 15 to said signal processing device. 20/25 30. 35 BAD ORIGINAL 8R η η ς o r