NL8200782A - Planarising the surface of semiconductor bodies with grooves - by applying thin 1st layer, thicker 2nd layer which fills grooves and 3rd layer in liq. form, and non selective etching - Google Patents

Abstract

Prodn. of a semiconductor device using a process for planarising a semiconductor body with grooves in the surface, in which a layer of a material in the liq. state is formed on the semiconductor body to give a configuration with a practically flat surface, after which non-selective etching is carried out in which the applied layer is removed together with part of the underlying material. Process include (1) coating the non-flat surface of the semiconductor with a relatively thin first layer contg. a first material (I) and which only partially fills the grooves and (2) applying a relatively thick second layer contg. a second material (II) different to (I) and which completely fills the grooves, (3) applying a third layer comprising a material (III) in the liq. state, (4) hardening the third layer and (5) subjecting the prod. to non-selective etching such that the third layer is completely removed, parts of the second layer remain in the grooves and the first layer is left practically intact. Process gives semiconductor devices such as integrated circuits with a flat surface, which favours very fine manufacturing tolerances so that higher packing densities can be achieved. The process is esp. useful for filling grooves in bipolar circuits in which grooves are formed in a silicon body to form electrically insulating islands in an epitaxial layer.

Description

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PHN 10284 Γ N.V. Philips' Incandescent light factories in Eindhoven.

"A method of manufacturing a semiconductor device and a semiconductor device manufactured by using this method".

The invention relates to a method of manufacturing a semiconductor device using a process for planarizing a grooved surface of a semiconductor body in which a layer of a material is in a liquid state on the semiconductor body. is formed to obtain a configuration with a practically flat surface, after which this layer is removed together with a part of the underlying material by means of a non-selective etching treatment.

The invention furthermore relates to a semiconductor device manufactured by using such a method.

The aforementioned flat surface forming process is known, inter alia, from AC Mams's article "Plasma Planarization", published in "Solid State Technology, April 1981, pp. 178/181. This article describes a process in which a layer P-doped glass 15 is deposited on a substrate whose surface is uneven due to the presence of a polycrystalline silicon strip The unevenness continues in said glass layer so that it has a step-shaped top surface. a photoresist layer in liquid form applied in such a composition that the photoresist layer and the P-glass layer are non-selectively etchable with respect to each other, ie can be etched off at the same speed in one and the same etching treatment. a configuration with a practically flat top surface can be obtained by subsequently using an ni et-25 selective etching treatment to completely remove the photoresist layer, the P-glass is also attacked at the location of the tap-shaped elevation where the lacquer layer is thinner. When the photoresist layer has been completely removed, the step-shaped elevation in the glass layer is also wholly or practically completely removed, so that a substantially flat surface is obtained.

Most preferably, when manufacturing integrated circuits, the surface of the semiconductor body is as flat as possible. In order to achieve a high packing density, it is important to manufacture the wire pattern connecting the circuit elements as finely as possible and with the lowest tolerances possible. A non-flat surface generally limits minimum tolerances. Often the surface is just not flat, due to grooves provided for special purposes extending from the surface into the silicon body. In bipolar circuits, for example, grooves may be provided to form electrically insulated islands in an epitaxial layer. In the islands, circuit elements are arranged which are interconnected by conductor tracks formed on the surface which, as the grooves completely surround the islands, cross grooves.

The object of the invention is to provide a method for manufacturing a semiconductor device in which the surface of a grooved semiconductor body is practically completely leveled.

A method according to the invention is characterized in that first the non-planar surface of the semiconductor body is covered with a relatively thin first layer comprising a first material and only partially filling the grooves, and that on the first layer a relatively thick second layer is formed which contains a second material, different from the first, and which fills the grooves completely, and that said layer is applied as a third layer in the liquid state in the liquid state, and that after the third layer has hardened said etching treatment is carried out, which is continued as long as the third layer has been removed, parts of the second layer still remain in the grooves, and that the first, the bottom, layer is at least practically unaffected.

The invention will be further elucidated on the basis of an exemplary embodiment and the accompanying schematic drawing in which

Fig. 1 shows a top view of part of an integrated circuit manufactured by applying a method according to the invention;

Fig. 2 shows a section of the device along the line II-II;

Fig. 3-10 show the same sections along the line II-II at different stages of the device;

It is noted that the figures are schematic and not drawn to scale.

Although the invention is applicable not only in bipolar circuits but also in other types of semiconductor devices, the following exemplary embodiment concerns an integrated bipolar circuit 8200782 c & PHN 10284 3 --- because of the particular importance of the invention for this type - semiconductor devices.

i

The device of FIG. 1 and 2 comprises a semiconductor body of a conventional composition, having a p-type silicon substrate 2 and an n-type epitaxial silicon layer 3 adjoining the surface 1 adjacent to the interface between the epitaxial layer 3 and the substrate 2 channel-bounding zones 5 are of the same conductivity type as the substrate but with a higher doping concentration, and low-impedance n-type buried zones 4. In the epitaxial layer 3, 10 islands 6 are formed which are separated from each other by the island insulation pattern 7. In the drawing, only the one in the center of Fig. 1 located island, shown in full, while only parts of the adjacent islands are visible. Circuit elements of the integrated circuit such as transistor and diodes, resistors, and other elements known per se and required for a specific circuit are arranged in the islands. For example, in the centrally drawn island 6, a bipolar transistor is provided with an n-type emitter 8, a p-type base 9, and an n-type collector comprising the 4 + island 6, the n-buried layer 4 and an n-type collector contact zone 10.

20 Via contact windows, in Fig. 1 shown in broken lines, the emitter 8 and base 9, and the collectors 4,10 are connected to resp. an emitter terminal 11, a base terminal 12, and a collector terminal 13 connecting the transistor to other circuit elements or contact surfaces for external terminal conductors.

The island insulation pattern forms a dielectric insulation where the upright edges of the islands 5 are adjacent to a dielectric material. This form of island insulation has important advantages over the more common pn insulation, in which the islands are electrically insulated from each other by intermediate pn junctions biased in the reverse direction. In the latter form of island insulation, the base 8 must be located at a relatively great distance from the island insulation. With dielectric insulation, on the other hand, as shown in Fig. 1 and 2, the base can be arranged directly next to or near the island insulation, whereby an important saving of space can be obtained.

The island insulation 7 is formed by a pattern of grooves i extending from the surface 1 into the epitaxial layer 3. The walls of the groove are covered with insulating material (14,15,16) which can be 8200782 PHN 10284 4 9 + ------- simply a layer of silicon oxide only, but in the present embodiment two layers 14 and 16, which contains silicon oxide and an intermediate layer of silicon nitride, but which may also consist of other materials. flat top surface is obtained. This allows the conductor tracks 11, 12 and 13 crossing the island insulation to be produced in fine patterns with small tolerances, which can further increase the packing density of the circuit.

To the. hand of fig. 3-10, a method according to the invention for manufacturing the circuit according to FIG. 1 and 2.

A p-type substrate 2 is assumed, with a resistivity between 2 and 5 ohms. cm. and <1.1.1> crystal orientation. In the usual manner, n Tzones doped on the surface of the substrate Sb are formed at the locations of the buried collector zones 4 in the finished device. Then, by means of a maskless doping step, the p-type doping on the surface of the substrate 20 can be increased to obtain the channel-interrupting zones 5. The concentration of this doping step is so low that the n-zones applied for this purpose 4 are not overdosed.

The layer 3 is then applied to the substrate by means of epitaxy. The thickness and the specific resistance of the layer 3 are, for example, 5 µm and respectively. 1.0 ohm.on. The n-type contact zone 10 is first formed by means of masked diffusion of phosphor. At the same time, the Sb partly diffuses into the epitaxial layer so that at the interface between the epitaxial layer 3 and the substrate 2, the buried collector zone 4 connected to the n-type contact zone 10 is obtained. The oxide mask used for this diffusion can then be removed, after which an approximately 0.6 µm thick oxide layer 18 is grown by thermal oxidation on the surface 1 of the epitaxial layer 3. In places where the base c.g. the collector contact window will be formed at a later stage, windows are provided in the oxide layer 18 which are again closed by the much thinner oxide layers 19. The situation as in FIG. 3 is then received. The thickness of the oxide layer 19 is, for example, 0.1 µ unu

Then, an approximately 0.15 µm thick silicon 8200782 PHN 10284 5 * nitride layer 20 (Fig. 4) and, for example, an approximately 1.5 µm thick layer 21 of Al are applied. Another layer, for example SiO2, can also be applied instead. On the Al layer 21, a photocask 21 of, for example, a photoresist layer is formed, which defines the location of island isolation 7. By means of anodic oxidation, for example in an oxalic acid solution, the part of the Al layer 21 not covered by the photoresist 22 is then converted into A 2 O 2.

After the oxidation, the photomask 22 can be removed again. After that, maskless, can. in a plasma etching of, for example, CCl, the unreacted Al of the layer 21 and the silicon nitride layer 17 are removed, and, for example, by conventional wet etching, the underlying parts of the oxide layer 10. Now a mask has been obtained which defines the location of the insulation pattern 7 in the epitaxial layer 3.

A groove 23 is then formed in the epitaxial layer 3, for example by means of etching with a CCl 2 plasma, at the location of the insulation pattern 7. The groove 20 extends. into the channel stopper zone 5 (Fig. 5) to a depth of, for example, about 6 µm. In the present exemplary embodiment, the groove 23 is U-shaped with practically upright walls. In the example shown in FIG. 1 drawn configuration form the group.

20 and 23 ditches, which define a rectangular island, and intersect at the corners of the islands. For example, the width of the groove 23 along the _____ sides of the rectangles is about 5 µm (groove 23a in Fig. 5). The diameter of the intersections in the ditches at the corners of the islands (groove 23b in Fig. 5) is, at that width, approximately 25 è. 10 µm.

It is noted that instead of a U shape, the grooves may also have a different shape, for example a V shape. However, because of the higher packing density, U-shaped grooves will often be preferred.

In a next step, the A 2 O 2 layer 21 can be removed, for example, by dissolving in a mixture with phosphoric acid. Thereafter, the walls and the bottom of the grooves 23a, 23b are covered by thermal oxidation with the oxide layer 14 (Fig. 6) having a thickness of about 0.5 µm. During this oxidation step (locos), the silicon body 35 is locally masked against oxidation by the nitride layer 20. Thus, the oxide (14) on the wall is much thicker than the oxide 19 on the top surface.

Partly because of this, it is later possible to make holes to the top surface without locally removing the oxide from the side wall of the groove.

8200782 · »* EHN 10284 6 - In those cases where it is necessary or desired to apply a -------- substrate contact to the top of the semiconductor body, then using the usual photo- masking techniques, the oxide layer 14 is removed locally at least along the wall 5 of the groove 23. This step is not shown in the drawing. Plasma etching then allows the. silicon nitride layer 20 are removed. Then the basic window is opened by a dip-etch. At the same time, a layer of the oxide layers 18 and 14 is removed, but this is not a problem because the oxide 19 is much thinner than the layers 14, 10 and 18. Boron deposition / diffusion then takes place via the windows thus obtained to obtain of the p-type base 9 (Fig. 7).

Where the oxide layer 14 was removed along the wall of a groove 23, a p-type bonding zone (not shown in the drawing) along the wall of the groove may be formed between the p-type regions 2.5 and the surface 1. pine formed. After or during the drilling position / diffusion, the base window is closed again by the oxide layer 24 with a thickness of approximately 0.1. Then, the silicon nitride layer 15, with a thickness of about 0.15 µm, and, by means of deposition, the oxide layer 16 (TEOS) with a thickness of, for example, Q..5 µm, are then applied (Fig. 7).

As shown in Fig. 8, the oxide layer 16 is applied to fill the grooves 23a, 23b again. The layer 25 here consists of polycrystalline silicon, but it will be clear that other materials can also be used instead. The poly is preferably applied by the per se known LPCMH method (low-pressure chemical vapor deposition), by decomposing silane or other suitable starting material at a temperature of about 70 ° C at low pressure (1 Torr). . The poly grows equally on the oxide in all directions, so that at a layer thickness of about 2 µm, the groove 23a is practically completely filled. Deposition is continued until groove 23b is filled to above layer 16. At the location of narrow groove 23a, the poly has only a slight depression. At the corners of the islands, on the other hand (23b), the poly Si has a relatively large pit due to the large width of the groove in that area.

To finally obtain a flat or at least practically flat surface, groove 23b is filled to the top of layer 16. A layer 26Y of "one" material in a liquid state with a sufficiently low viscosity is then applied to the layer of "25", so that an almost practical flat top surface 27 8200782 -------; -, ------- ^ BHN 10284 7 - is obtained For the layer 26, a material should be enjoyed which ------ with an equal or at least practically equal etch rate during the same etching treatment can be removed as the underlying poly-silicon layer 25. In the exemplary embodiment discussed here, a photoresist layer, commercially available under the name HPR 204, was used for the layer 26. The thickness of the layer 26 is not critical and is between 1.5 and 2 µm. An etching treatment is then carried out using, for example, a CCl 2 plasma, whereby the photoresist layer 26 and the polysilicon layer 25 are attacked at approximately the same speed.

When the photoresist layer 26 has been removed above the islands and the groove 23a, the polysilicon at the location of the groove 23b is still masked by a remainder of the photoresist layer. As a result, the polysilicon will only be attacked at a later stage in those places where the surface of the layer 25 is at a lower level than in other places.

FIG. 9 shows the device at the stage that the polysilicon above the islands has been completely removed, while the remaining polysilicon still fully or at least practically completely fills the groove 23a, 23b and forms the polysilicon parts 17. It should be noted here that the level of the poly in the groove 23b is just as, or at least practically, the same height as in the groove 23a, so that a substantially flat top surface is obtained. the silicon oxide layer 16 to be exposed again, which itself again protects the underlying nitride layer 15 against attack in the plasma. The attendant change of the reaction products in the plasma reactor can be used as a measure of when the etching can be stepped.

In a next step, the silicon oxide layer 16, as far as at least not covered by the polysilicon parts 17, is removed. Preferably, an oxidation step is carried out for this etching step, in which an approximately 0.5 µm thick oxide layer is grown on the polysilicon parts 17. During the etching of the layer 16, this oxide is also removed again, so that the level of the polysilicon parts is reduced by approximately 0.25 µm and step-coating problems can be avoided at a later stage. The poly can then optionally be doped to obtain a low resistivity. During the etching of the oxide 16, the oxide layers 14 and 18 were protected by the nitride layer 15.

In a next step, the nitride layer 15 is patterned by means of photocask and etching (Fig. 10), with above, the island 5, the emitter window, the base contact window, and the collector contact window are defined by the silicon nitride parts, respectively. 28, 29 and 30. By means of a locos oxidation, the surface which is not masked by the nitride parts then becomes relatively thick. oxide 31 has grown. At the same time, pp polysilicon parts 17 also grow an oxide layer.

The nitride layers 28 and 30 are then removed by means of a non-critical photocask masking the nitride 29, after which the thin oxide can be removed under the nitride layers 28 and 30 by means of unmasked dipets. A phosphor diffusion is made via the emitter-10 ter and collector contact windows thus obtained, to obtain the emitter 8 and a collector contact zone. Then, by removing the nitride layer 29 and the thin oxide below, the base contact window is opened. made.

If necessary, locally. the oxide above the polysilicon 15 is opened to make a connection to the polysilicon. Such a connection is not shown in the drawing. If this poly-Si also makes electrical contact with the substrate, the substrate can in this way be contacted at the top of the semiconductor device. It is also possible to give the poly-Si such an electrical potential that channel formation in regions along the groove (e.g. 5 and 9) is prevented.

The emitter connection 11, the base connection 12, and the collector connection 13 can be applied in the usual manner by evaporation and pattern etching of, for example, Al, or another suitable material (Fig. 2). Thanks to it. Almost flat surface, the joints crossing the island insulation pattern can be applied as a fine pattern with great precision. And because the dimensions of the conductor tracks can be small, and because space is saved by using dielectric island insulation, the circuit 30 can be designed with a high packing density.

It will be clear that the invention is not limited to the exemplary embodiment described here, but that many variations are still possible for the skilled person within the scope of the invention. For instance, for the etching of the photoresist layer 26 and the underlying polysilicon layer 25, instead of CCl, other halogen-containing gases can be used, with or without the addition of an oxidant, also carbon fluoride, with the addition of O2. Instead of the photoresist layer - other layers with sufficiently low viscosity, such as 8200782 ESN 10284 9 φ ____polimida layers, can be used. The grooves can also be filled -------- with, for example, polyimide. instead of polycrystalline silicon 17.

The planarization method used in this case differs from the described method in that instead of the poly-silicon layer 25, a polyimide layer is applied. In that case, the oxide layer 16 and / or the nitride layer 15 can optionally be omitted if, when the polyimide layer is etched with the planarising layer above (e.g.

HPR 204), a plasma, for example using an oxygen plasma that does not attack other layers. The advantage is thereby obtained that this layer 10 can be adhered in a more or less liquid state (and can be cured after application, by heating), so that the surface of the layer is already considerably flatter than that of, for example, the vapor-deposited layer 25. It should be noted that since polyimide is not resistant to very high temperatures, the application of the polyimide layer and the subsequent planarization method. must take place after all thermal treatments, such as oxidation steps and / or diffusion steps. Instead of a liquid photoresist layer 26 is also possible. a low solid state can be used which, after application, is temporarily brought into liquid state, and, after a flat top surface 27 has been obtained, can be brought back into solid state.

25 30 1 8200782

Claims (13)

1. A plasticization method for manufacturing a semiconductor device using a process for planarizing a grooved surface of a semiconductor body in which a layer of a material in the liquid state is formed in the semiconductor body to form a configuration with a practically flat surface after which this layer is removed together with a part of the underlying material by means of a non-selective etching treatment, characterized in that first the non-planar surface of the semiconductor body is covered with a relatively thin first layer which first material and only partially fills the grooves, and that on the first layer a relatively thick second layer is formed which contains a second material, different from the first, and fills the grooves completely, and that the second layer in said layer liquid state when the third layer is applied, and that after the third has hardened The layer, the said etching treatment is carried out, which is continued for as long as the third layer is completely removed, parts of the second layer still remain in grooves, and that the first, the bottom, layer is at least practically unaffected. Method according to claim 2, characterized in that said etching treatment is stopped when the second layer has been completely removed in places between the grooves, so that a practically flat surface is obtained which is formed at the location of the grooves by the remaining parts of placing the second layer and pp between the grooves by parts of the first layer. Method according to claim 1 or 2, characterized in that a semiconductor body of silicon is used and that a layer of silicon oxide is applied as the first layer. 4. A method according to claim 3, characterized in that said second layer is applied in the form of a polycrystalline silicon layer. Method according to claim 4, characterized in that the polycrystalline silicon layer is applied by means of an LPCVD technique. A method according to claim 4 or 5, characterized in that a semiconductor body is used in the form of a substrate provided with a surface-contiguous surface layer separated from the substrate by at least one p-n junction, and in which a number of mutually insulated islands is defined by means of said grooves 8200782 PHN 10284 11) - in which switching elements are arranged. - Method according to claim 6r, characterized in that the substrate and the surface layer are of mutually opposite conductivity type. Method according to claim 6 or 7, characterized in that the surface layer is applied to the substrate by means of epitaxial growth. 9. A method according to any one of claims 6 to 8, characterized in that in at least one of said islands a bipolar transistor is formed with three superimposed zones of alternating conductivity, an emitter and a collector zone of the one conduction type and an intermediate base zone of the second conduction type, wherein at least the pn junction between the base zone and the collector zone is adjacent or at least practically adjacent to the upright wall of one of said grooves. 9 PHN 10284 10 Method according to one or more of the preceding claims, characterized in that the grooves are arranged in the form of intersecting U-shaped locks of practically uniform cross-section. Method according to claim 1, characterized in that said first layer is applied at least partly in the form of a layer 20 of silicon oxide. A method according to claim 11, characterized in that said silicon oxide layer is obtained by oxidizing the walls of the groove by local oxidation, the remainder of the surface being masked against oxidation. 13. Process according to claim 11 or 12, characterized in that a layer of silicon nitride is applied to said layer of silicon oxide, after which a second partial layer of silicon oxide is applied over the entire surface of the nitride layer from the vapor phase, parts of which are etchings of the second layer, not covered by the remaining parts of the second layer, are removed again. 1 8200782