NL8001686A - METHOD AND APPARATUS FOR TESTING THE PROCESSOR CONTROL UNIT OF AN MOTOR VEHICLE ANTI-LOCKING SYSTEM. - Google Patents

Description

Ή. O. 28775, h ..

Method and device for testing the processor control unit of an anti-lock device of a motor vehicle.

The invention relates to simulation testing of an anti-lock system, and more particularly relates to a method and apparatus for in-simulation testing of an anti-lock system as used for a motor vehicle.

Motor vehicles are nowadays manufactured with anti-lock or anti-skid systems for steering the skid. Such an anti-lock braking system typically includes a sub-assembly associated with each wheel of the motor vehicle for converting pivotal movement into the electrical signal, an arithmetic control unit, and a sub-assembly associated with each brake of the motor vehicle for converting an electrical signal in brake pressure. Each rotatable motion-electrical signal converter subsystem 15 outputs an electrical signal that is frequency-related in its pulses to the rotatable motion of the associated wheel. These signals are read and interpreted by a processor control unit which signals when a slip is indicated to the electrical signal-to-brake converter transducers to properly adjust the braking pressure and thereby the braking action of the slipping wheels to block or reduce.

In at least such a system, as manufactured and sold by Eobert Bosch GmbH, the processor control unit generates a pressure release signal when the frequency of the input signal falls below the frequency of the input signal of other wheels and further decreases therefrom. The computer controller also generates a press-50 hold signal when the frequency is low but increases.

With a rear wheel, the pressure release and pressure hold signals have a relatively long duration. On the front wheels, however, these signals are so short that accurate measurement of their size is practically impossible.

In the past, testing with the Bosch control unit was performed by electronically simulating the simultaneous skidding of all four wheels of the motor vehicle. Since the simulation of this condition does not accurately reveal the front wheel response, it has long been sought for a better test.

The invention therefore relates to a method and an apparatus for testing the processing or processor control unit of an anti-blocking system for a motor vehicle. First, a substantially fixed frequency signal is applied to the inputs of the processor control unit. The essentially fixed frequency signal is then maintained at a selected input and a decreasing frequency signal is simultaneously applied to the remaining inputs. The processor control unit is thereby forced to temporarily take the essentially fixed frequency signal at the selected input as a reference signal and thereby react to the selected input in order to output a fixed pressure signaling signal when the output the frequency of the signal at the selected input is below the substantially fixed frequency of the fixed frequency signal and decreases, and in order to deliver a fixed pressure hold signal at the output when the frequency of the signal at the selected input is below the essentially fixed frequency of the signal with essentially fixed frequency lies and increases.

Then, a signal is applied to the selected input at a frequency that gradually decreases from the substantially fixed frequency signal when the processor controller has temporarily adopted the fixed frequency signal. The amplitude of the pressure release signal is measured simultaneously.

Then, a signal is applied to the selected input at a frequency that gradually increases to the fixed frequency also while the processor control unit has temporarily adopted the fixed frequency signal. The amplitude of the pressure hold signal is measured simultaneously.

55 As a result of this procedure, the response of the processor control unit can be accurately tested regardless of whether the pressure release and pressure hold signals are normally short as well.

Another object of the invention is to provide an apparatus for implementing the above-mentioned 8001686 1 * -3 method.

It is also an object of the invention to provide a method and apparatus which are particularly suitable for testing the front wheel response of a processor control unit as manufactured and sold by Robert Bosch GmbH.

Another object of the invention is to provide a method and apparatus for remote electronic testing which is fast, very accurate and economical. The invention will be further elucidated on the basis of a preferred embodiment with reference to the drawings, in which:

Fig. 1 shows a diagram of the preferred embodiment according to the invention; and FIG. 2 shows a graph of the preferred method and operation of the preferred device according to the invention.

In Fig. 1, the preferred embodiment of the invention is indicated by a device indicated by 10 for testing simulation of a motor vehicle anti-lockout system (ABS) generally indicated by 12.

For display purposes, the anti-lock system 12 includes an ABS processor 14, four rotatable motion-electrical converters (RM-ES converters) 16, 18, 20, 25, 22, and four electrical signal-hydraulic brake transducers ( ES-HBP) converters) 24, 26, 28, 50. Each converter 16, 18, 20, 22 responds to the rotational motion of a motor vehicle wheel to generate an electrical signal in response, and each converter 24, 26 , 28, 30 responds to an electrical signal to generate a hydraulic pressure change for a motor vehicle brake. The ABS processor 14- receives and processes the electrical signals from the RM-ES converters 16, 18, 20, 22 and appropriately signals to the ES-1BP converters 24, 26, 28, 30.

More specifically, the RM-ES converter 16 responds to the right front wheel RFW of the motor vehicle; the RM-ES converter 18 responds to the left front wheel LFW; the RM-ES converter 20 responds to the right rear wheel RRV and the RM-ES converter 22 responds to the left rear wheel.

4-0 wheel LRW. The RM-ES converters contain tacho 8001686, respectively. * 4-meter generators 32 5 34, 36, 38. Each tachometer generator 32, 34, 36, 38 senses the rotation of its associated motor-vehicle wheel RFW, LEW, RRW, LRW, respectively, and generates a simis signal in response. The frequency 3 of the sinusoidal signal is proportional to the frequency of wheel rotation.

The ES-IIBP converter 24 controls the right front brake REB; the ES-HBP converter 26 controls the left front brake LEB; the ES-IIBP transducer 28 controls the right rear brake REB; and the ES-IIBP transducer 30 controls the left rear brake LRB. The ES-IBP converters 24, 26, 28, 30 include brake control valves 40, 42, 44, 46, respectively. Each brake control valve 40, 42, 44, 46 responds to three different voltage level input signals and has three corresponding valve settings. The input of a first or "pressure unpressurized" voltage level places the control valves 40, 42, 44, 46 in a "brake unpressurized" state. The pilot valves 40, 42, 44, 46 are biased in this state, which permits the unpressurized application of the brakes by the motor vehicle operator, i.e. the rider. The supply of a second or "pressure release" voltage level places the control valves 40, 42, 44, 46 in "pressure release" condition. In this condition, the use of the brakes by the operator is not allowed, and it is not permitted to The use of a third or "pressurized" voltage level places the control valves 40, 42, 44, 46 in a "pressurized" condition which overrides the full brake operator's operation but allows partial braking.

The ABS processor 14 receives and compares the sinusoidal signals from the RM-ES converters 16, 18, 20, 22. When the signals received from one or more of the RM-ES converters 16, 18, 20, 22 are lower in frequency than those of the remaining RM-ES converters 16, 18, 20, 22 received 35 signals, the ABS processor 14 a signal for the particular ES-1BP converters among the ES-1BP converters 24, 26, 28, 30 which control the brakes of the wheels from which the low-frequency signals are received. When the RM-ES converter signal decreases in frequency, the ABS processor 40 sensor 14 issues a pressure release signal; when the RM-ES converts 8001686 -5- *, t signal increases, the ABS processor 14 issues a hold signal.

For example, when the left front wheel LFW slips while the rider brakes, the turning frequency of the left 5 front wheel LFW decreases compared to that of the other wheels EEW, LEW, EEW, The signal frequency of the EM-ES converter 18 decreases proportionally, and this acceptance is received by the ABS processor 14. The ABS processor 14 in response delivers a pressure release input signal to the ES-HBP converter 26 which releases the pressure for the left front brake LEB, allowing the left front wheel LEW to increase its rotational speed.

The increasing rotational speed is then sensed by the EM-ES converter 18, and the ABS processor 14 in response delivers a pressure attitude input signal to the ES-HBP converter 15 26 which partially brakes the left front brake LEB.

With an ABS processor 14, such as the B 265 100 005 from Eobert Bosch GmbH, the pressure release and pressure maintenance signals of the ABS processor are stable for the rear brake converters 28 and 30 and extremely short for the front brake converters 24.26.

20 The difference apparently relates to the steering action or the motor vehicle responsiveness to the front wheel versus rear wheel slip movements.

As stated, the device 10 is intended for in-simulation testing of the ABS processor 14. The device 25 supplies simulated EM-ES converter signals to the inputs of the ABS processor 14 and monitors the output signals of the ABS processor.

The simulated EM-ES converter signals are applied to the inputs 50, 52, 54, 56 of the ABS processor 14, respectively via the cables 58, 60, 62, 64 of the device 10. The processor outputs 66, 68, 70, 72 are monitored via the cables 74, 76, 78, 80 of the device 10, respectively. As a first step in testing the ABS processor 14, a test operator connects the cables 58, 60, 35, 62, 64, 74, 76, 78, 80 to their proper inputs and outputs.

Preferably, the cables 58, 60, 62, 64, 74, 76, 78, 80 are bundled and a connection is made to a conventional multiple plug-bus connector. The cables 58, 60, 62, 64 are connected to the outputs of a multiplexer 82, 40 controlled by a processor 84. The multiplexer 82.80 0 1 6 86 -6- receives signals from a signal source 86 and from a voltage controlled oscillator 88. The processor 84 instructs the multiplexer 82 in response to instructions from an operator control panel 90, such as a keyboard. pass signal 5 from source 86 to one or more cables 58, 60, 62, 64 and to pass signal / decoder 88 to the remaining cables.

The source 86 generates an essentially uniform sinusoidal signal. Preferably, the frequency of the source 86 is 2500 Hertz,

The oscillator 88 also generates a sinusoidal signal. The frequency of the oscillator 88 is variable in proportion to a control signal received at the oscillator input 94. Preferably, the oscillator 88 generates signals within a range of frequencies including 2500 Hertz and 1000 Hertz.

The oscillator 88 is controlled by the processor 84 by means of a 12-bit locking circuit 96 and a digital-analog converter 98. The processor 84 generates oscillator control data which passes through the data bus 100 to the input 96a-1 of the lock switch. The processor authorizes the lock controller 96 through a lock enable input 102. Therefore, an instruction from the processor 84 sets the lock controller 96 according to the data at its inputs 96a-1.

The digital-analog converter 98 is connected via the data bus 104 to the latch outputs 96m-x and converts the digital data from the lock circuit 96 into an analog signal. This analog signal is applied to input 94 50 of the oscillator,

The signals from the signal source 86 and from the oscillator 88 are monitored by the processor 84 by means of a feedback circuit generally designated 104. The circuit 104 includes a multiplexer 106, a counter lock-55 divider 108, a clock 110, and a counter enable-counter reset-counter sampling control unit 112. A first input line 114 connected to a first input 116 of the multiplexer 106 and between the source 86 and the multiplexer 82 outputs the signal from the signal source 86 to the multiplexer 106. A second input line 118, which 8001686 -7-

X

connected to the second input 120 of the multiplexer 106 and between the oscillator 88 and the multiplexer 82, the signal from the oscillator 88 outputs the multiplexer 106.

The waveforming stages 122 along the input lines 114, 118 form the sinusoidal signals from the source 86 and the oscillator 88 into block shapes with equivalent periods. The multiplexer 106 therefore receives block-shaped input signals. The waveforming stages 122 are of a conventional nature and have a shaping effect by zero-exceedance detection 10 or the like.

The control lines 124 connect the processor 84 and the multiplexer control inputs 126.

The output of the multiplexer 106 is applied to the input of the control unit 112. The control unit 112 responds to the increasing (or decreasing) edges of the pulses of the multiplexer 106, and in particular responds to the increasing (or decreasing) ) edge of the first pulse after an extended delay between the pulses.

In particular, the controller 112 responds to a first pulse by outputting a "reset" output signal to the counter reset input 150 of the counter lock circuit 108 through an output 128, and outputting an "enable" output signal through the output 152. gate 154. Gate 154 connects the clock 110 to the counter input 156 of the counter lock circuit t 108. When the output signal from the output 152 is received, the gate 154 connects the clock 110 to the counter input 156. Therefore, the tank lock circuit 108 counts from zero the pulses from the clock 110.

The controller 112 responds to the rising edge of the first and of each successive pulse by outputting a "sampling" signal through the output 157 to the processor input 138 of the processor 84 and a latch set input 140 of the counter latch 108 The sig-35 sew on the lock adjustment input 140 sets the lock of the counter lock circuit 108 to the current count position. The signal at the processor input 15S causes the processor 84 to read the lock of the counter lock circuit 108 via data bus 142. The processor 84 stores the 40 lock data or count position in a memory 144.

8001686 -8-

Thus, the feedback circuit 104 and the processor 84 cooperate to measure and store raw data with respect to the time periods of pulses from the source 86 and the oscillator 88. The processor 84 compares pairs of successive counts and calculates the difference in counting positions to determine the time periods of pulses in units of clock pulses.

The frequency of the clock 110 is stored in the memory 144. Preferably, the frequency of the clock 10 is equal to 20 MHz. The processor 84 converts the time periods of the pulses as measured in units of clock pulses into units of seconds, or any other desired time unit.

The processor 84 compares the time periods of the pulses as calculated with stored data indicating desired time periods. The processor 84 sets the data delivered to the latch circuit 96 according to the difference between the measured time periods and the desired time periods.

The device 10 can therefore accurately simulate different slip states to test the ABS processor 14. The device 10 simulates testing the ABS processor 14 as follows.

After the cables 58, 60, 62, 64, 66, 68, 70, 72 are connected, the test operator informs the device 10 through the operator control unit 90 to start testing.

The device 10 then proceeds to test the response of the ABS processor 14 to subsequent simulated slip movements of the motor vehicle wheels LFW, RFW, LEV, RRw. Slip movements of each wheel of the four wheels LFW, RFW, LRW, RRW are simulated identically. Therefore, only the simulation of a slip of the left front wheel LFW is described.

To begin this simulation, the processor 35 84 signals the multiplexer 82 to output the signal from the signal source 86 to all four cables 58, 60, 62, 64, as shown in the interval A of FIG. 2. The ABS processor 14 has therefore been started, the ABS processor 14 interprets the adjusted frequency signals as a non-slip movement 40 of the wheels RFW, LFW, RRW, LRW and is ready to slip. 8001686-9. , weighing responses. At this time, the processor 84- also instructs the multiplexer 106 to output the signal from the signal source 86. The processor 84 tests the periods of pulses from the signal source 86 as counted by the counter latch 108, and uses the resulting information to select initial data for the latch 96.

The processor 84 then instructs the multiplexer 82 to deliver the signal from the signal source 86 to the cable 60 and to deliver the signal from the oscillator 88 to the remaining cables 85, 82, 64. The processor 84 essentially outputs simultaneously transfer the selected data to the latch circuit 96. The processor 84 also authorizes the latch circuit 96, thereby starting the oscillator 88. The initial output to the latch circuit 96. data sets the oscillator frequency to the frequency of the signal source.

The processor then instructs the multiplexer 106 to output the signal from the oscillator 88, and then 20 'sets the data supplied to the latch circuit 96 according to the actual output of the oscillator 88.

The data processor 84 maintains the instruction for the multiplexer 82 and simultaneously and repeatedly revises the data delivered to the latch circuit 96, permitting the latch circuit 96 when new data is issued. The revised data lowers the frequency of the oscillator 88 and outputs a decreasing sawtooth signal to the cables 58, 62, 64 as indicated by interval B or FIG.

While the instruction for the multiplexer 82 is held, the processor 84 issues an increasing sawtooth signal to the cables 58, 62, 64 once a pulse period of preselected duration from the data of the counter 35 lock switch 108 has been measured. This operating interval is indicated in Fig. 2 as interval B. Preferably, the preselected time period corresponds to an eVn-thousand Hertz signal from the oscillator 88. Also, preferably, the frequency increasing and frequency decreasing intervals 40 of the interval B are approximately equal and keep about 800 1 6 86 \ -10 - {one second on.

The decrease of the frequencies on the cables 58? 82, 64 during interval B is interpreted by the ABS processor 14 as a slipping movement of the three wheels EFW, 5 RRW, LEW. Thus, the ABS processor 14 is forced to take as its reference signal the signal of substantially fixed frequency supplied by cable 60 to input 52. Because of this constraint, the device 10 forces the ABS processor 14 to respond to its input signal 52 to issue sustained pressure release and hold pressure signals regardless of whether it was programmed to issue such resistant signals or to output only short-lived signals. to give. This state persists for a short time after the signals for inputs 15, 50, 54? 56 are equal to the signal for input 52 as indicated by the interval C of FIG. 2. In Robert Bosch's processor control unit B 265 100 005, this state lasts about a quarter of a second.

Within the time interval C, the processor 84 issues a new instruction to the multiplexer 82. This instruction instructs the multiplexer 82 to output the signal from the signal source 86 to the three cables 58, 62, 64 and. to output the signal from the oscillator 88 to the cable 60. The processor 84 essentially begins simultaneously transmitting data and power signals for the latch circuit 96 to apply a decreasing sawtooth signal to the cable 60. The sawtooth signal is maintained for a time interval D and is followed by an increasing sawtooth signal for the time interval E.

After the ABS processor 14 is forced to take the signal at input 60 as a reference, the ABS processor 14 responds to the decreasing sawtooth signal with a steady pressure release signal and to the increasing sawtooth signal with a steady pressure hold signal. During the expected duration of these signals, the processor 84 measures the amplitude of the signals and displays them on the video display 146. The operator can therefore sense the strength of the signals and take action when necessary.

8001686 -11- t

In the device 10, the time intervals D and E together are preferably a total of about three seconds and the low frequency of the signal applied to the cable 60 is 1000 Hertz. Preferably, the inter-5 traps D and E immediately precede and follow each other. Any delay of less than a quarter of a second can be tolerated, but a longer delay allows the ABS processor 14 to release the signal at input 60 and transition to non-resistant pressure release and 10 hold down signals.

8001686

Claims (2)

A method of testing the processor control unit of a motor vehicle anti-lockout system, which method comprises steps of applying a substantially fixed frequency signal to the inputs of the processor control unit, maintaining the signal with the essentially fixed frequency to a selected input and simultaneously supplying a decreasing frequency signal to the remaining inputs forcing the processor control unit to temporarily adopt the signal of substantially fixed frequency as the reference signal and thereby / start responding to the selected input signal to output a steady pressure release signal at the output when the frequency of the signal at the selected input is below the frequency of the signal of substantially fixed frequency and decreases, and to maintain a steady pressure —Signal when the frequency of the signal at the selected input is below the frequency of the sign substantially fixed frequency and the supply of a signal to the selected input is increased by a frequency which gradually decreases relative to the frequency of the substantially fixed frequency signal while the processor control unit is temporarily supplying the signal with essentially adopted a fixed frequency and simultaneously measuring the amplitude of the pressure release signal; and applying a signal to the selected input at a frequency that gradually increases to the fixed frequency while the processor controller has temporarily assumed the fixed-frequency signal, and simultaneously measuring the amplitude of the hold pressure signal. 30 2. Device for testing the processor control unit in a motor vehicle anti-lock device provided with means for supplying a substantially fixed frequency signal to the inputs of the processor control unit, means for maintaining the signal at substantially fixed frequency to a selected input and simultaneously supplying a decreasing frequency signal to the remaining inputs forcing the processor control unit to temporarily take the substantially fixed frequency signal as the reference signal at the selected input, 8001686 -13- N # ^ and thereby react to the selected input signal to output a steady pressure release signal when the frequency of the signal at the selected input is below the frequency of the signal of substantially fixed frequency and decreases, and to steady a steady pressure hold signal when the frequency of the signal at the selected input is below the frequency v the signal is of substantially fixed frequency and increases; means for supplying a signal to the selected input with a frequency gradually decreasing from the frequency of the substantially fixed frequency signal while the processor controller has temporarily adopted the fixed frequency signal and simultaneously measuring the amplitude of the pressure release signal, and means for supplying a signal to the selected input with a frequency gradually increasing towards the fixed frequency while the processor control unit has temporarily adopted the fixed frequency signal and simultaneously measuring the amplitude of the pressure hold 20 signal. 8001686