MXPA06008326A - A two channel bus structure to support address information, data, and transfer qualifiers - Google Patents

Abstract

Various methods and processing systems are disclosed which include sending and receiving components communicating over a bus having first and second channels. The sending component may broadcast on the first channel a plurality of read and write address locations, a plurality of transfer qualifiers, and write data. The receiving component may store the write data broadcast on the first channel at the receiving component based on the write address locations and a first portion of the transfer qualifiers. The receiving component may also retrieve read data from the receiving component based on the read address locations and a second portion of the transfer qualifiers, and broadcast the retrieved read data on the second channel.

Description

A TWO CHANNEL BUS STRUCTURE TO SUPPORT ADDRESS INFORMATION, DATA AND TRANSFER CALIFORITIES Field of the Invention The present disclosure generally relates to digital systems, and more specifically, to a two-channel bus structure capable of supporting address information, data and transfer qualifiers.

BACKGROUND OF THE INVENTION Computers have revolutionized the electronics industry by allowing sophisticated processing tasks to be performed with only a few keystrokes. These sophisticated tasks involve an incredibly high number of complex components that communicate with each other in a fast and efficient way using a bus. A bus is a channel or path between components in a computer. A typical computer includes a microprocessor with system memory. A high bandwidth system bus can be used to support communications between the two. In addition, there may also be a lower performance peripheral bus that is used to transfer data to lower bandwidth peripherals. In some cases, there may also be a configuration bus that is used for the purpose of scheduling various resources. Bridges can be used to efficiently transfer data between higher and lower bandwidth buses, as well as to provide the necessary protocol interpretation. Many buses resident on a computer have traditionally been implemented as shared buses. A shared bus provides a means for any number of components to communicate over a common path or channel. In recent years, bus sharing technology has been replaced to a greater degree by point-to-point switched connections. The point-to-point switched connections provide a direct connection between two components on the bus while they are communicating with each other. Multiple direct links can be used to allow several components to communicate at the same time. Conventional bus designs include independent and separate channels for reading, writing and addressing. A microprocessor, for example, can read or write to the system memory by placing a location address in the address channel and by sending the appropriate read / write control signal. When the microprocessor writes data to the system memory, it sends the write channel data. When the microprocessor reads the data from the system memory, it receives the data on the read channel. Although this particular bus structure provides a regularly standardized way to communicate between components of a computer, it requires a number of dedicated channels. These channels require controller, receiver and circuits. intermediate memory, of which all consume energy. In integrated circuit applications, these channels occupy valuable area for chips. Accordingly, there is a need in the art for a simplified bus structure.

SUMMARY OF THE INVENTION In one aspect of the present invention, a method for communicating between a sending component and a receiving component on a bus includes broadcasting from the sending component on a first channel a plurality of read and write address locations. , a plurality of transfer qualifiers, and write data. The receiving component stores the broadcast of write data in the first channel based on the write channel locations and a first portion of the transfer qualifiers. The receiving component also retrieves read data from the receiving component based on the read location addresses and a second portion of the transfer qualifiers, and broadcasts the read data retrieved in the second channel. In another aspect of the present invention, a processing system includes a bus having first and second channels. A sending component is configured to broadcast a plurality of read and write address locations in the first channel., a plurality of transfer qualifiers, and write data. A receiving component is configured to store the broadcast of write data in the first channel based on the write address locations and the portion of the transfer qualifiers. The receiving component is also configured to retrieve read data based on the read address locations and a second portion of the transfer qualifiers, and diffuses the read data retrieved in the second channel. In still another aspect of the present invention, a processing system includes a bus having first and second channels. The processing system also includes means for broadcasting in the first channel a plurality of read and write address locations, a plurality of transfer qualifiers, and write data. The processing system further includes means for storing the broadcast of write data in the first channel based on the write address locations and a first portion of transfer qualifiers, retrieving the read data based on the read address locations and a second portion of the transfer qualifiers, and disseminate the read data retrieved in the second channel. It is understood that other embodiments of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein various embodiments of the invention are shown and described by way of illustration. As will be seen, the invention is capable of other and different embodiments and its various details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention. Accordingly, the drawings and detailed description will be taken as illustrative in nature and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present invention are illustrated by way of example and not by way of limitation, in the accompanying drawings, in which: FIGURE 1 is a conceptual block diagram illustrating an example of a point connection to point between two components in a processing system on a two-channel bus; FIGURE 2 is a conceptual block diagram illustrating an example of a point-to-point connection between two components in a two-channel bus processing system capable of supporting address, data and transfer qualifiers information; FIGURE 3 is a timing diagram showing two parallel reading operations on a two-channel bus capable of supporting address information, data and transfer qualifiers; FIGURE 4 is a timing diagram showing three parallel reading operations on a two-channel bus capable of supporting address information, data and transfer qualifiers; and FIGURE 5 is a timing diagram showing read and write operations on a two-channel bus capable of supporting address information, data and transfer qualifiers.

DETAILED DESCRIPTION OF THE INVENTION The detailed description set forth in the following with the accompanying drawings is intended as a description of various embodiments of the present invention and is not intended to represent the only embodiments in which the present invention may be practiced. Each mode described in this description is provided only as an example or illustration of the present invention, and should not necessarily be taken as preferred or advantageous over other modalities. The detailed description includes specific details for the purpose of providing a complete understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form in order to avoid obscuring the concepts of the present invention. Acronyms and other descriptive terminology may be used only for convenience and clarity and are not intended to limit the scope of the invention. FIGURE 1 is a conceptual block diagram illustrating an example of a point-to-point connection on a bus between two components in a processing system. The processing system 100 may be a collection of cooperating components to perform one or more processing functions. Typically, the processing system will be a computer, or it will be resident in a computer and will be able to process, retrieve and store information. The processing system 100 is shown with a sending component 102 in communication with a receiving component 104 on a bus 106. In a mode of the processing system 100, the bus 106 is a dedicated bus between the sending component 102 and the reception component. In another embodiment of the processing system 100, the sending component 102 communicates with the receiving component 104 with a point-to-point connection on the bus 106 through a bus interconnection. (not shown). In addition, as those skilled in the art will readily appreciate, the inventive aspects described throughout this description are not limited to a dedicated bus or point-to-point switching connection, but can be applied to any type of bus terminology that includes, by example, a shared bus. The sending component 102 can be any type of bus mastering component that includes, by way of example, a microprocessor, a digital signal processor (DSP), a direct memory access controller, a bridge, a logical component. programmable, discrete transistor logic gate, or any other information processing component.

The receiving component 104 may be any storage component, which includes, by way of example, registers, memory, a bridge, or any other component capable of retrieving and storing information. The storage capacity at each address location of the receiving component may vary depending on the particular application and the overall design constraints. For purposes of explanation, the receiving component will be described with a storage capacity of 1 byte per address location. The complexity of the bus 106 can be reduced by eliminating the address channel that is used in conventional bus structures. Deletion of the address channel can be achieved by redefining the structure channel as a "transmission channel" 108. The transmission channel 108 can be used as a generic means for disseminating information between the sending component 102 and the receiving component 104. a multiplexed form by time division. This information may include address information, writing data, transfer qualifiers, or any other information related to the bus. The term "transfer qualifier" refers to a parameter that describes an attribute of a read operation, write operation or any other operation related to the bus. A "group of transfer qualifiers" refers to one or more transfer qualifiers associated with a single read operation, write operation, or other operation related to the bus. Examples of transfer qualifiers include a read / write signal, a payload size signal, a byte enable signal, a burst transmission signal, transfer indication labels, a security signal, and a attribute that can be cached. Each of these transfer qualifiers will be discussed in greater detail later. Those skilled in the art will readily understand that the transfer qualifiers used in current implementations may vary depending on the specific application and the general design constraints. The transfer qualifiers used in these implementations may include any combination of one or more transfer qualifiers described in the above and / or any other signal parameter that describes an attribute of any operation related to the bus. In at least one mode of the bus 106, both the transmission channel 108 and the read channel can be 64 bits wide with 8-byte paths. This allows the sending component 102 to broadcast up to 8 bytes of write data on the transmit channel 108 and the receive component 104 to broadcast up to 8 bytes of read data on the read channel 110. In addition, the sending component 102 may be capable of simultaneously broadcasting a 32-bit address and up to 32 bits of transfer qualifiers on the transmission channel 108 as conceptually illustrated in FIGURE 2. With reference to FIGURE 1, the component The sending 102 may perform any operation related to the bus that includes reading, or writing to, the receiving component 104. In the case where the sending component 102 writes to the receiving component 104, the sending component can broadcast an address location together with a group of transfer qualifiers on the transmission channel 108 followed by a payload. The term "payload" refers to data associated with a single read or write operation. In this casp, the transfer qualifiers may include a "read / write signal" to indicate a write operation, and a "payload size signal" to indicate the number of bytes of data contained in the payload. If the payload is multi-byte, then the receiving component 104 may store the payload in a block at sequential address locations beginning with the address location broadcast on the transmission channel 108. By means of the example, if the sending device 102 broadcasts an address location 100HEX followed by a payload of 4 bytes, the receiving component 104 may write the payload in a block of address locations starting at 100HEX and ending at 103HEX- In the In the case where the sending component 102 reads from the receiving component 104, the address location and the associated group of transfer qualifiers may be the only information it needs to broadcast on the transmission channel 108. The transfer qualifiers may include a "read / write signal" to indicate a read operation, and a "payload size signal" to indicate the number of bytes of data contained in the payload. multi-byte, then the receiving component 104 can read the payload of a block of sequential address locations beginning with the address location broadcast on the transmission channel 108. By way of example, if the sending device 102 spreads a 200HEX address location and requests a payload of 4 bytes, the receiving component 104 can retrieve the payload from a block of address locations that starts at 200HE? and ends at 200HEX- In addition to the read / write signals and the payload size, a group of transfer qualifiers can include a byte enable signal, the "byte enable signal" can use is to indicate which byte paths will be used to spread the payload. By means of the example, a 4-byte payload broadcast on the transmission channel 108 or the read channel 110 can use tracks 4 of the 8 bytes. The byte enable signal for a write operation can be used to indicate to the receiving component 104 which of the 4-byte channels in the transmission channel 108 will be used to broadcast the payload. Similarly, the byte enable signal for a read operation can be used to indicate to the receiving component 104 in which of the 4-byte channels in the read channel 110 it expects to receive the payload in the sending component. The group of transfer qualifiers may also include a burst transmission signal. The "burst transmission signal" can be used to indicate whether the payload will be broadcast in a single transmission or in a burst. A "single transmission" occurs when the entire payload is broadcast on the transmit and read channel 108 and 110 in a single clock cycle. In this way, a single transmission can be used to broadcast an 8-byte payload with all byte paths enabled. A "burst transmission", on the other hand, occurs when the payload is broadcast on the transmission channel 108 or on the read channel 110 over multiple clock cycles. In this way, a burst transmission may be needed to broadcast a payload with more than 8 bytes. An implicit address scheme can be used to control the broadcast sequence of read and write data on the transmission and reading channels 108 and 110. By way of example, if the sending component 102 initiates a write operation by broadcasting an address location with the appropriate read / write signal in the transmission channel 108, then the payload for that write operation may be broadcast in the transmission channel 108 before a new write operation is initiated. If on the other hand, the sending component 102 initiates multiple read operations by broadcasting the appropriate read / write signals and multiple address locations, the receiving component 104 can retrieve the data in the same sequence in which it receives the locations of address. "Transfer identification indicators" can be used as an alternative for an implicit address scheme. The sending component 102 can assign a transfer identification label for each read and write operation. The transfer identification tag may be broadcast on the transmission channel 108 together with the address location associated with the read or write operation. In the case of a write operation, the sending component 102 can send the transfer identification tag with the payload, and the receiving component 104 can use the transfer identification tag retrieved from the appropriate group of transfer qualifiers to identify the payload. In the case of a read operation, the receiving component 104 can send the transfer identification tag retrieved with the payload, and the sending component can use the transfer identification tag to identify the payload. Any type of transfer qualifier is an "attribute signal that can be cached". The attribute signal that can be cached can be used in the case where a microprocessor accesses the system memory through a cache memory. In this case, the sending component 102 is the microprocessor and the receiving component 104 is the cache memory. If the cache detects an attribute signal that can be saved in cached memory, you can try to read the data from the cache or write the data to the cache depending on whether a read or write operation is being required. If the microprocessor requests a read operation and the data is not cached, then the cache memory can retrieve the data from the system memory, and cache the recovered data before sending it to the microprocessor. A security signal is another type of transfer qualifier. The "security signal" can be used to indicate whether the payload is data or an instruction. The security signal can also be used to grant access to a bus mastering device for a particular memory resource. The various concepts described in this way so far can be implemented using any number of protocols. In the detailed description that follows, an example of a bus protocol will be presented. This bus protocol is being presented to illustrate the inventive aspects of a processing system, with the understanding that the inventive aspects can be used with any suitable protocol. The basic signaling used for this protocol is shown in the following in Table 1. Those skilled in the art will easily be able to vary and / or add signals to this protocol in the current implementation of the bus structure described herein. TABLE 1 Signal Definition Carried out by Clock the clock signal of Reference System Processing A Valid a valid address that is Broadcast Component in the Send channel Transmission Confirmation indicates that the Component component of Receive is capable of receiving Transfer accept a request to perform a read or write operation 64-bit bus channel for Component of Transmission broadcasting address information, transfer qualifiers and write data to the reception component Confirmation indicates the component of Write component reception that is capable of receiving accept write data 64 bit bus channel for Component of Reading broadcast reading dice reception to the sending component Confirmation confirmation for the Reading Component sending component that the receiving component reception is broadcasting reading data in the Reading Channel FIGURE 3 is a timing diagram showing two operations of reading in parallel on a channel bus two channels capable of supporting address information, data and transfer qualifiers. A System Clock 302 can be used for synchronizations between the sending component and the receiving component. System Clock 302 is shown with fourteen cycles, with each cycle numbered by sequences for ease of explanation. A read operation can be initiated by the sending component during the second clock cycle 303 by asserting the signal 304 A Valid. Concurrently with the assertion of the signal 304 A Valid, the sending component may broadcast an address location and an associated group of transfer qualifiers with a first read operation Rx on the Transmission Channel 308. The transfer qualifiers may include a read / write signal and a payload size signal, which together notify the receiving component that the sending component is requesting a 32-byte read operation. Transfer qualifiers can also include a transmission signal in rSphaga and a byte enable signal. In this case, the signals can be set to indicate to the receiving component that the payload should be broadcast as a burst transmission that extends over four clock cycles using all byte paths of the 64-bit read channel 312. Transfer qualifiers can also include a transfer identification label that the receiving component can send with the payload. A security token can also be included in the transfer qualifiers to grant access to the reception component. In the case of a broadcast from a microprocessor to the system memory, an attribute signal that can be cached can also be included in the transfer qualifiers. When the reception component detects the assertion of the signal 304 A Valid, it can sample the address information and the associated group of transfer qualifiers from the transmission channel 308. The receiving component can determine from the read / write signal, the payload size signal, the burst transmission signal, and the byte enable signal that the device is requesting a 32 byte read operation. to spread in a burst transmission and extending over four clock cycles in all the byte paths of Channel 312 of Reading. In the case where the receiving component is a cache, the receiving component can also check the transfer qualifiers for an attribute signal that can be cached. The receiving component can also determine whether the sending component is authorized to access the read data when checking the security signal. If the safety signal is not affirmed, the receiving component can send a signal again to the sending component indicating that it is not authorized to read data. Assuming that the security token is properly asserted, the receiving component can begin to retrieve data at the appropriate address locations. The receiving component may also assert a transfer confirmation signal 306 indicating that it received the broadcast. In this case, the Transfer Confirmation signal 306 is continuously asserted. At the end of the second clock cycle 306, the sending component can detect the assertion of the Transfer Confirmation signal 306, and respond upon starting another read operation. This can be achieved by asserting the signal 304 A Valid and broadcasting an address location and an associated group of transfer qualifiers with a second read operation R2 on the Transmission Channel 308. The transfer qualifiers may again include signaling notifying the receiving component that the sending device is authorized to initiate a 32-byte read operation and that the payload reading of the receiving component should be broadcast in a burst transmission that is extends over four clock cycles in all byte paths of Channel 312 of Reading. A transfer identification tag, a security token and / or an attribute signal that can be cached can also be included in the transfer qualifiers. When the reception component detects the assertion of the signal 304 A Valid, it can sample the address information and the associated group of transfer qualifiers from the Transfer Channel 308. Assuming that the security token is asserted, the receiving component can begin to retrieve data at the appropriate address locations. The receiving component can also affirm the Transfer Confirmation signal 306 indicating that it received the broadcast. Once the sending component detects the Transfer Confirmation signal 306 at the end of the third clock cycle 305, it can challenge signal 304 A Valid in the fourth clock cycle 307, indicating to the receiving component that a read operation or Writing will not be requested. Due to the read latency of the receiving component, a diverse clock cycle delay may be experienced before the read data can be provided with the Reading Channel 312. In this case, the first 8 bytes of the payload Rx (1) associated with the first read operation Rx can be retrieved from the receiving component and broadcast in the Read Channel 312 during the sixth clock cycle 311, the second 8 bytes of the payload R? (2) associated with the first read operation i can be recovered from the receiving component and broadcast on the reading channel 312 during the seventh clock cycle 313, the third 8 bytes of the payload R? ( 3) associated with the first read operation Rx can be recovered from the receiving component and broadcast on the reading channel 302 during the eighth clock cycle 315, and the final 8 bytes of the payload R? (4) associated with the first Rx reading operation can be recovered from the reception component and broadcast in Reading Channel 312 during the ninth clock cycle 317. The corresponding transfer identification label can be sent with each 8-byte broadcast. During this broadcast of the fourth clock cycle, the receiving component can assert the Reading Confirmation signal 314 to indicate to the sending component that it is broadcasting read data in Reading Channel 312. In a similar manner, the payload R2 (l), R2 (2), R2 (3) and R2 (4) associated with the second reading operation R can be recovered from the receiving component and broadcast in Reading Channel 312 during the tenth, eleventh, twelfth and thirteenth cycles 319, 321, 323 and 325 of the clock. During this broadcast of the fourth clock cycle, the reception component may keep the Confirmation signal 314 of Reading asserted to indicate to the sending component that it is broadcasting data in the Reading Channel 312. FIGURE 4 is a timing diagram showing three read operations in parallel on a two-channel bus capable of supporting address, data and transfer qualifiers information. The two read operations described previously together with FIGURE 3 are repeated in FIGURE 4 and therefore will not be discussed further. An additional read operation may be initiated by the sending component in the fourth clock cycle 307 by broadcasting an address location R3 and an associated group of transfer qualifiers with a third read operation R3 on the Transmission Channel 308. Transfer qualifiers may again include signaling that notifies the receiving component that the sending device is authorized to initiate a 32-byte read operation, and that the payload reading of the receiving component should be broadcast in a burst transmission which extends over four clock cycles in all the byte paths of Channel 312 of Reading. A transfer identification tag and / or an attribute signal that can be cached can also be included in the transfer qualifiers. During the same clock cycle, the receiving component can defy the Transfer Confirmation signal 306 which indicates that it can not currently accept the broadcast since, by way of example, its address queue is full. The sending component can detect that the Confirmation 306 Transfer signal is not asserted at the end of the fourth clock cycle 309. In response, the sending component may continue to broadcast the address location and the associated group of transfer qualifiers with the third read operation R3 on the Transmission Channel 308 until the sending component detects a Confirmation signal 306 of the reception component. In this case, the broadcast continues in the fifth, sixth and seventh cycles 309, 311 and 313 of the clock. During the seventh cycle 313, the reception component may be able to recover a broadcast on the Transmission Channel 308 and perform the requested operation, as indicated by the affirmation of the Transfer Confirmation signal 306. In response to the Confirmed Transfer confirmation signal 306, the sending component may determine that it no longer needs to broadcast the address location and the associated group of transfer qualifiers with the third read operation R3 during the eighth clock cycle 315, and can defy the signal 304 A Valid. Alternatively, the sending component may queue the broadcast for the address location and the associated group of transfer qualifiers with the third reading operation R3 when it detects that the Transfer Confirmation 306 signal is not asserted at the end of the fourth cycle. 307 clock The broadcast may be queued until the receiving component indicates that it is ready to accept a broadcast on the Transmission Channel 308 by asserting the Transfer Confirmation 306 signal. In this case, the sending component can monitor the Transfer Confirmation signal 306 until it is asserted by the reception component in the seventh clock cycle 313. When the sending component detects that the Transfer Confirmation signal 306 is asserted at the end of the seventh clock cycle 313, it can broadcast the queued address location and the transfer qualifier group over the Transmission Channel 308 in the eighth cycle 315 of clock. During the fifth, sixth and seventh cycles 309, 311 and 313 of the clock, the sending component can broadcast new address locations and appropriate groups of transfer qualifiers on the Transmission Channel 308, or disseminate any remaining data to write to the reception component. Returning to FIGURE 4, the receiving component may be able to recover a broadcast on the Transmission Channel 308 and perform the requested operation on the seventh cycle 313 of the clock. More specifically, the receiving component can sample the address information and the associated group of transfer qualifiers of the Transmission Channel 308. Assuming that the security signal is asserted, the receiving component can begin to recover the payload associated with the third read operation R3. The first 8 bytes of the payload R3 (l) associated with the third reading operation R3 can be recovered from the receiving component and broadcast in the reading channel 312 during the fourteenth clock cycle 327, the second 8 bytes of the payload R3 (2) associated with the third reading operation R3 can be recovered from the receiving component and broadcast in Reading Channel 312 during the fifteenth clock cycle 329, and the third 8 bytes of the payload R3 (3) associated with the third reading operation R3 can be recovered from the receiving component and broadcast in Reading Channel 312 during the sixteenth clock cycle 331, and the final 8 bytes of payload R3 (4) associated with the third read operation R3 can be recovered of the reception component and broadcast in Reading Channel 312 during the seventeenth cycle 333 of the clock. The corresponding transfer identification label can be sent with each 8-byte broadcast. During this fourth clock cycle broadcast, the receiving component can keep the Confirmation signal 314 from Reading asserted to indicate to the sending component that it is broadcasting the reading data in the Reading Channel 312. FIGURE 5 is a timing diagram showing read and write operations on a two-channel bus capable of supporting address information, data and transfer qualifiers. A read operation can be initiated by the sending component during the second clock cycle 303. This can be achieved by asserting the signal 304 A Valid and broadcasting an address location and an associated group of transfer qualifiers with a first read operation Rx on the Transmission Channel 308. The transfer qualifiers may include signaling that notifies the receiving component that the sending device is authorized to initiate a 32-byte read operation, and that the payload reading of the receiving component must be broadcast in a burst transmission that is It spreads over four clock cycles in all the byte channels of Channel 312 of Reading. A transfer identification tag and / or an attribute signal that can be cached can also be included in the transfer qualifiers. When the reception component detects the assertion of the signal 304 A Valid, it can sample the detection information of the associated group of transfer qualifiers of the Transmission Channel 308. Assuming that the security signal is asserted, the receiving component can begin to recover the payload associated with the first read operation Rx. The receiving component may also affirm a Transfer Confirmation signal 306 indicating that it has received the broadcast. The sending component can detect the Transfer Confirmation signal 306 at the end of the second clock cycle 303. Sensitive to the Transfer Confirmation signal 306, the sending component can challenge signal 304 A valid during the third clock cycle 305 indicating to the receiving component that it will not be sending address information and transfer qualifiers on Channel 308 of Transmission. In the fifth clock cycle 309, the sending component can initiate a write operation by asserting signal 304 A Valid and broadcasting an address location and associated group of transfer qualifiers with a first write operation Wx on Channel 308 of Transmission. Transfer qualifiers may include signaling that notifies the receiving component that the sending device is authorized to initiate a 32-byte write operation, and that the payload will be broadcast in a burst transmission that extends over four clock cycles in all the byte paths of the Transmission Channel 308. A transfer identification tag and / or an attribute signal that can be cached can also be included in the group of transfer qualifiers. When the reception component detects the signal 304 A Valid, it can sample the address information and the associated group of transfer qualifiers of the Transmission Channel 308. In response to the transfer qualifiers, the receiving component can assert the Transfer Confirmation signal 306 indicating that it has received the broadcast. The receiving component can also assert the Write Confirmation signal 310 which indicates that it is ready to write the payload in the appropriate block of sequential address locations. In the sixth clock cycle 311, the sending component may begin broadcasting the payload on the Transmission Channel 308. Diffusion can be initiated by defying signal 304 A Valid and broadcasting in the Transmission Channel 308 the first 8 bytes of the payload Wx (l) associated with the first write operation Wx. The receiving component can receive the first 8 bytes of the payload x (l) in the appropriate block of sequential address locations. Concurrently, the first 8 bytes of the payload Rx (l) associated with the first read operation Rx can be retrieved from the receiving component and broadcast in the Read Channel 312 with the corresponding transfer identification tag. The receiving component can also keep the Confirmation signal 314 from Reading asserted by indicating that it is sending read data in the Read Channel 312. With the Write Confirmation signal 310 still asserted at the end of the sixth clock cycle 311, the sending component can broadcast on the Transmission Channel 308 the second 8 bytes of the payload x (2) associated with the first operation Wx of writing. The receiving component can write the second 8 bytes of the payload Wx (2) in the appropriate block of sequential address locations. Concurrently, the second 8 bytes of the payload Rx (2) associated with the first read operation Rx can be retrieved from the receiving component and broadcast in the Read Channel 312 with the corresponding transfer identification tag. The receiving component can also keep the Confirmation signal 314 from Reading asserted by indicating that it is sending the reading data in the Reading Channel 312. In the eighth clock cycle 315, the sending component may temporarily suspend the broadcast of the write data to initiate a new read operation. This can be achieved by asserting the signal 304 A Valid and broadcasting an address location and an associated group of transfer qualifiers with a second read operation R2 on the Transmission Channel 308. The transfer qualifiers may include signaling that notifies the receiving component that the sending device is authorized to initiate a 16-byte read operation, and that the payload reading of the receiving component should be broadcast in a burst transmission that is it extends over the two clock cycles in all the byte paths of the Reading Channel 312. A transfer identification tag and / or an attribute signal that can be cached can also be included in the transfer qualifiers. During the same eighth clock cycle 315, the third 8 bytes of the payload Rx (3) associated with the first read Rx operation can be recovered by the receiving component and broadcast on reading channel 312 with the identification tag. of corresponding transfer. The receiving component can also keep the Confirmation signal 314 from Reading asserted by indicating that it is sending read data in the Read Channel 312. When the reception component detects the signal 304 A Valid at the end of the eighth cycle 315 clock, can sample the address information and associated group of transfer qualifiers of Transmission Channel 308. Assuming that the security signal is asserted, the receiving component can begin to recover the payload associated with the second read operation R2. The receiving component can also assert a Transfer Confirmation signal 306 indicating that it has received the broadcast. Simultaneously, the broadcast component can broadcast in the Read Channel 312 the final 8 bytes of the payload Rx (4) associated with the first read operation Rx with the corresponding transfer identification tag. The receiving component can also keep the Confirmation signal 314 from Reading asserted by indicating that it is sending read data in the Read Channel 312. In the same ninth clock cycle 317, the sending component can defy the signal 304 A Valid which indicates to the receiving component that the sending component will assume the broadcast of data in the Transmission Channel 308. With the Confirmation Write signal 310 of asserted writing, the sending component can broadcast on the Transmission Channel 308 the third 8 bytes of the payload x (3) associated with the first write operation W2. The receiving component can write the third 8 bytes of the payload in the appropriate block of sequential address locations. With the spread of the final 8 bytes of the payload Rx (4) associated with the first read operation Rx, the receiving component has completed the read operation initiated by the sending component during the second clock cycle 303. Therefore, the receiving component can challenge the Reading Confirmation signal 314 in the tenth clock cycle 319. Due to the read latency of the receiving component, it may not be ready to broadcast the payload associated with the second reading operation R2. With the Write Confirmation signal 310 still asserted in the tenth clock cycle 319, the sending component can broadcast on the Transmission Channel 308 the final 8 bytes of the payload x (4) associated with the first write operation x . The receiving component can write the final 8 bytes of the payload in the appropriate block of sequential address locations. With this broadcast, the indicated write operations are complete, and therefore, the receiving component can challenge the Write Confirmation signal 310 in the next clock cycle 321. In the twelfth clock cycle 323, the first 8 bytes of the payload R2 (l) associated with the second read operation R2 can be recovered from the receive component and broadcast in the Read Channel 312. In the next clock cycle 325, the final 8 bytes of the payload R2 (2) associated with the second read operation R2 can be retrieved from the receive component and broadcast in Read Channel 312. At the end of the payload broadcast, the receiving component can challenge the Reading Confirmation signal 314 in the fourteenth clock cycle 327. The ability of the processing system to broadcast the address information in the middle part of a write operation that spans multiple clock cycles may depend on the buffering capabilities of the sending and receiving components. In at least one embodiment of the processing system, the sending component can be implemented by a programmable means to enable or disable this feature based on the potential performance advantages or the supported buffering capabilities. The various illustrative logic blocks, modules and circuits described in conjunction with the embodiments described herein may be implemented or implemented with a general purpose processor, a digital signal processor (DSP)., a specific application integrated circuit (ASIC), a field programmable gate arrangement (FPGA) or other programmable logic component, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described in the present. A general purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing components, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors together with a DSP core, or any other configuration. The methods or algorithms described in conjunction with the embodiments described herein may be represented directly in hardware in a software module executed by a processor, or in a combination of the two. A software module may reside in a RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. A storage medium can be coupled to the processor so that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium can be an integral part of the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in the terminal, or in some other place. Alternatively, the processor and the storage medium may reside as discrete components in the terminal, or some other place. The prior description of the described embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited in the embodiments shown herein but must be in accordance with the broadest scope consistent with the principles and novel features described herein.

Claims (41)

1. NOVELTY OF THE INVENTION Having described the present invention, it is considered as a novelty and therefore the property described in the following claims is claimed as property. CLAIMS 1. A method for communicating between a sending component and a receiving component on a bus, the bus comprises first and second channels, the method characterized in that it comprises: broadcasting the sending component on the first channel of a plurality of locations of read and write address, a plurality of transfer qualifiers, and write data; storing the broadcast of write data on the first channel in the receiving component based on the write address locations and a first portion of the transfer qualifiers; recovering read data from the receiving component based on the read receipt locations and a second portion of the transfer qualifiers; and broadcast the readout data recovered in the second channel from the reception component. The method according to claim 1, characterized in that the transfer qualifiers comprise a plurality of transfer qualifier groups, each of the transfer qualifier groups comprising one or more of the transfer qualifiers, and wherein each of the transfer qualifier groups is broadcast on the first channel concurrently with a different one of the address locations. The method according to claim 2, characterized in that the receiving component stores a portion of the write data based on the group of transfer qualifiers and the address location contained in a concurrent broadcasts. The method according to claim 3, characterized in that the receiving component stores the portion of the write data in a sequential address location block starting with the address location contained in one of the concurrent broadcasts. 5. The method of compliance with the claim 3, characterized in that one of the transfer qualifiers in the group of transfer qualifiers contained in one of the concurrent broadcasts comprises a read / write signal indicating a write operation. 6. The method according to claim 3, characterized in that one of the transfer qualifiers in the group of transfer qualifiers contained in one of the concurrent broadcasts comprises a payload size indicating the number of bytes contained in the portion of the data. of writing. The method according to claim 6, characterized in that the second of the transfer qualifiers in the group of transfer qualifiers contained in one of the concurrent broadcasts comprises a burst transmission signal to indicate the number of clock cycles that the sending component will use to disseminate the portion of the write data, and where the third of the transfer qualifiers in the group of transfer qualifiers contained in one of the concurrent broadcasts comprises a byte enable signal to indicate the number of bytes of the write data that will be broadcast by the sending component during each of the clock cycles. 8. The method of compliance with the claim 3, characterized in that one of the transfer qualifiers in the group of transfer qualifiers contained in one of the concurrent broadcasts comprises a transfer identification label for identifying the portion of the write data. 9. The method according to claim 2, characterized in that the receiving component retrieves a portion of the read data based on the group of transfer qualifiers and the address location contained in one of the concurrent broadcasts. 10. The method according to claim 9, characterized in that the receiving component retrieves a portion of the read data from a block of sequential address locations that begins the address location contained in one of the concurrent broadcasts. The method according to claim 9, characterized in that one of the transfer qualifiers in the group of transfer qualifiers contained in one of the concurrent broadcasts comprises a read / write signal indicating a read operation. The method according to claim 11, characterized in that one of the transfer qualifiers in the group of transfer qualifiers contained in one of the concurrent broadcasts comprises a payload size signal indicating the number of bytes contained in the portion of the reading data. The method according to claim 12, characterized in that the second of the transfer qualifiers in the group of transfer qualifiers contained in one of the concurrent broadcasts comprises a burst transmission signal to indicate the number of clock cycles that the reception component will use to broadcast the portion of the read data, and where the third of the transfer qualifiers in the group of transfer qualifiers contained in one of the concurrent broadcasts comprises a byte enable signal to indicate the number of bytes of the read data that will be broadcast by the receiving component during each of the clock cycles. The method according to claim 9, characterized in that one of the transfer qualifiers in the group of transfer qualifiers contained in one of the concurrent broadcasts comprises a transfer identification label to identify the portion of the read data. The method according to claim 2, characterized in that the first channel comprises a plurality of lines, the sending component broadcasts the address locations in a first portion of the lines and diffuses the transfer qualifier groups in a second portion. of the lines. The method according to claim 2, characterized in that one or more concurrent broadcasts in the first channel are broadcast concurrently with the broadcast of at least a portion of the read data retrieved in the second channel. The method according to claim 1, characterized in that at least a portion of the write data is broadcast in the first channel concurrently with the broadcast of at least a portion of the read data retrieved in the second channel. The method according to claim 1, characterized in that the sending component broadcasts the address locations, the transfer qualifiers, and the write data in the first channel in a time division multiplexed form. The method according to claim 1, characterized in that the writing data comprises a plurality of payloads, and wherein the sending component diffuses at least one of the write or read address locations between the first and second portions. of the payloads. 20. The method according to claim 1, characterized in that the transfer qualifiers comprise a plurality of read / write signals, a plurality of payload size signals, a plurality of burst transmission signals, a plurality of enabling signals. byte, a plurality of transfer identification tags, a plurality of security tokens, and a plurality of attribute signals that can be cached. 21. A processing system, characterized in that it comprises: a bus having first and second channels; a sending component configured to broadcast on the first channel a plurality of read and write address locations, a plurality of transfer qualifiers, and write data; and a receiving component configured to store the write data broadcast in the first channel based on the write address locations and a first portion of the transfer qualifiers, and where the receive component is further configured to retrieve read data based on in the reading address locations and a second portion of the transfer qualifiers, and broadcast the read data retrieved in the second channel. 22. The processing system according to claim 21, characterized in that the transfer qualifiers comprise a plurality of transfer qualifier groups, each of the transfer qualifier groups comprising one or more of the transfer qualifiers, and wherein the sending component is further configured to broadcast each of the transfer qualifier groups concurrently with a different one of the address locations. 23. The processing system according to claim 22, characterized in that the receiving component is further configured to store a portion of the write data based on the group of transfer qualifiers and the address location contained in one of the broadcasts. concurrent The processing system according to claim 23, characterized in that the receiving component is further configured to store the portion of the write data in a block of sequential address locations beginning with the address location contained in one of the concurrent broadcasts. 25. The processing system according to claim 23, characterized in that one of the transfer qualifiers in the group of transfer qualifiers contained in one of the concurrent broadcasts comprises a read / write signal indicating a write operation. 26. The processing system according to claim 23, characterized in that one of the transfer qualifiers in the group of transfer qualifiers contained in one of the concurrent broadcasts comprises a payload size signal indicating the number of bytes contained in the portion of the writing data. 27. The processing system according to claim 26, characterized in that the second of the transfer qualifiers in the group of transfer qualifiers contained in one of the concurrent broadcasts comprises a burst transmission signal to indicate the number of cycles of clock that the sending component will use to broadcast the portion of the write data, and where the third of the transfer qualifiers in the group of transfer qualifiers contained in one of the concurrent broadcasts comprises a byte enable signal to indicate the number of bytes of the write data that will be broadcast by the sending component during each of the clock cycles. The processing system according to claim 23, characterized in that one of the transfer qualifiers in the group of transfer qualifiers contained in one of the concurrent broadcasts comprises a transfer identification tag to identify the portion of the data of the transfer. writing. 29. The processing system according to claim 22, characterized in that the receiving component is further configured to recover a portion of the read data based on the group of transfer qualifiers and the address location contained in one of the concurrent broadcasts. 30. The processing system according to claim 29, characterized in that the receiving component is further configured to retrieve the portion of the read data from a block of sequential address locations beginning with the address location contained in one of the concurrent broadcasts. The processing system according to claim 29, characterized in that one of the transfer qualifiers in the group of transfer qualifiers contained in one of the concurrent broadcasts comprises a read / write signal indicating a read operation. 32. The processing system according to claim 31, characterized in that one of the transfer qualifiers in the group of transfer qualifiers contained in one of the concurrent broadcasts comprises a payload size signal indicating the number of bytes contained in the reading data portion. 33. The processing system according to claim 32, characterized in that the second of the transfer qualifiers in the group of transfer qualifiers contained in one of the concurrent broadcasts comprises a burst transmission signal to indicate the number of cycles of clock that the receiving component will use to broadcast the portion of the read data, and where the third of the transfer qualifiers in the group of transfer qualifiers contained in one of the concurrent broadcasts comprises a byte enable signal to indicate the number of bytes of the read data that will be broadcast by the receiving component during each of the clock cycles. 34. The processing system according to claim 29, characterized in that one of the transfer qualifiers in the group of transfer qualifiers contained in one of the concurrent broadcasts comprises a transfer identification label to identify the portion of the data of the transfer. reading. 35. The processing system according to claim 22, characterized in that the first channel comprises a plurality of lines, and where the sending component is further configured to broadcast the address locations in a first portion of the lines and broadcast the groups of transfer qualifiers in a second portion of the lines. 36. The processing system according to claim 22, characterized in that the send is further configured to be coupled to one or more concurrent broadcasts on the first channel at the same time that the broadcast component broadcasts at least a portion of the data of reading recovered in the second channel. 37. The processing system according to claim 21, characterized in that the sending component is further configured to broadcast at least a portion of the write data in the first channel at the same time that the receiving component broadcasts at least a portion of the read data retrieved in the second channel. 38. The processing system according to claim 21, characterized in that the sending component is further configured to broadcast the address locations, the transfer qualifiers, and the write data in the first channel in a time division multiplexed manner. 39. The processing system according to claim 21, characterized in that the writing data comprises a plurality of payloads and where the sending component is further configured to broadcast at least one of the write or read address locations between the first and second portions of one of the payloads. 40. The processing system according to claim 21, characterized in that the transfer qualifiers comprise a plurality of read / write signals, a plurality of payload size signals, a plurality of burst transmission signals, a plurality of of byte enabling signals, a plurality of transfer identification tags, a plurality of security tokens, and a plurality of attribute signals that can be cached. 41. A processing system, characterized in that it comprises: a bus having first and second channels; means for broadcasting in the first channel a plurality of read and write address locations, a plurality of transfer qualifiers, and write data; and means for storing the write data broadcast in the first channel based on the write address locations and a first portion of the transfer qualifiers, retrieving the read data based on the read address locations and a second portion of the transfer qualifiers, and disseminate the read data retrieved in the second channel.