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MXPA03008017A - Arreglo de computadoras tolerante a fallas y procedimiento para el funcionamiento de un arreglo de ese tipo. - Google Patents

Arreglo de computadoras tolerante a fallas y procedimiento para el funcionamiento de un arreglo de ese tipo.

Info

Publication number
MXPA03008017A
MXPA03008017A MXPA03008017A MXPA03008017A MXPA03008017A MX PA03008017 A MXPA03008017 A MX PA03008017A MX PA03008017 A MXPA03008017 A MX PA03008017A MX PA03008017 A MXPA03008017 A MX PA03008017A MX PA03008017 A MXPA03008017 A MX PA03008017A
Authority
MX
Mexico
Prior art keywords
cluster
processing
plane
fault
operating
Prior art date
Application number
MXPA03008017A
Other languages
English (en)
Inventor
Kaiser Oliver
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of MXPA03008017A publication Critical patent/MXPA03008017A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1691—Temporal synchronisation or re-synchronisation of redundant processing components using a quantum
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/183—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components
    • G06F11/184—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components where the redundant components implement processing functionality

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Measuring Or Testing Involving Enzymes Or Micro-Organisms (AREA)

Abstract

Se presenta un arreglo de computadoras de acuerdo con la invencion con un plano de red o comunicacion (10) y un plano de procesamiento (30), en el arreglo el plano de comunicacion esta formado por cuando menos una computadora de red (11, 12,13)la cual es capaz de asignar a los datos de entrada (7) con una marca de tiempo, el plano de procesamiento (30) esta formado por cuando menos dos computadoras de procesamiento (201, 202, 20x, 211, 212, 21y, 221, 222, 22z) las cuales reciben en paralelo desde el plano de comunicacion(10) los datos de entrada(7) y las computadoras de procesamiento estan cada vez capacitadas para procesar los datos de entrada (7) en el siguiente paso de procesamiento si el valor actual de la marca de tiempo cae en una zona de evaluacion significativa respectiva. De esta manera se realiza una sincronizacion implicita de las computadoras.
MXPA03008017A 2001-03-07 2002-02-28 Arreglo de computadoras tolerante a fallas y procedimiento para el funcionamiento de un arreglo de ese tipo. MXPA03008017A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP01105702A EP1239369A1 (de) 2001-03-07 2001-03-07 Fehlertolerante Rechneranordnung und Verfahren zum Betrieb einer derartigen Anordnung
PCT/EP2002/002181 WO2002071223A1 (de) 2001-03-07 2002-02-28 Fehlertolerante rechneranordnung und verfahren zum betrieb einer derartigen anordnung

Publications (1)

Publication Number Publication Date
MXPA03008017A true MXPA03008017A (es) 2004-05-24

Family

ID=8176710

Family Applications (1)

Application Number Title Priority Date Filing Date
MXPA03008017A MXPA03008017A (es) 2001-03-07 2002-02-28 Arreglo de computadoras tolerante a fallas y procedimiento para el funcionamiento de un arreglo de ese tipo.

Country Status (11)

Country Link
US (1) US7260740B2 (es)
EP (2) EP1239369A1 (es)
JP (1) JP3867047B2 (es)
CN (1) CN1262924C (es)
AT (1) ATE282855T1 (es)
DE (1) DE50201568D1 (es)
ES (1) ES2231677T3 (es)
MX (1) MXPA03008017A (es)
RU (1) RU2279707C2 (es)
WO (1) WO2002071223A1 (es)
ZA (1) ZA200304933B (es)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2408355B (en) * 2003-11-18 2007-02-14 Ibm A system for verifying a state of an environment
DE102004051952A1 (de) * 2004-10-25 2006-04-27 Robert Bosch Gmbh Verfahren zur Datenverteilung und Datenverteilungseinheit in einem Mehrprozessorsystem
JP4101251B2 (ja) * 2005-05-24 2008-06-18 富士通株式会社 負荷分散プログラム、負荷分散方法、及び負荷分散装置
US7644308B2 (en) * 2006-03-06 2010-01-05 Hewlett-Packard Development Company, L.P. Hierarchical timestamps
US9237034B2 (en) * 2008-10-21 2016-01-12 Iii Holdings 1, Llc Methods and systems for providing network access redundancy
RU2543316C2 (ru) * 2012-12-25 2015-02-27 Закрытое акционерное общество "Лаборатория Касперского" Система и способ отказоустойчивого выполнения задач по расписанию в распределенных средах
WO2016067420A1 (ja) * 2014-10-30 2016-05-06 三菱電機株式会社 計算機及びデータ処理方法及びプログラム
CN104461793A (zh) * 2014-12-05 2015-03-25 中国航空工业集团公司第六三一研究所 一种高可靠多节点容错计算机系统及同步方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4979108A (en) * 1985-12-20 1990-12-18 Ag Communication Systems Corporation Task synchronization arrangement and method for remote duplex processors
US4937741A (en) * 1988-04-28 1990-06-26 The Charles Stark Draper Laboratory, Inc. Synchronization of fault-tolerant parallel processing systems
SU1584137A1 (ru) * 1988-11-14 1990-08-07 Предприятие П/Я А-3890 Резервированна система
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
RU2010315C1 (ru) * 1991-04-24 1994-03-30 Государственный научно-исследовательский и конструкторский институт систем контроля и управления "Система" Резервированная система
US5339404A (en) * 1991-05-28 1994-08-16 International Business Machines Corporation Asynchronous TMR processing system
FR2700401B1 (fr) * 1993-01-08 1995-02-24 Cegelec Système de synchronisation de tâches répondantes.
JP3501305B2 (ja) * 1993-08-04 2004-03-02 サン・マイクロシステムズ・インコーポレイテッド 相互接続制御装置及び方法
JP3274058B2 (ja) * 1996-03-22 2002-04-15 富士通株式会社 光ディバイス
US5790397A (en) * 1996-09-17 1998-08-04 Marathon Technologies Corporation Fault resilient/fault tolerant computing
US5903717A (en) 1997-04-02 1999-05-11 General Dynamics Information Systems, Inc. Fault tolerant computer system
US5896523A (en) * 1997-06-04 1999-04-20 Marathon Technologies Corporation Loosely-coupled, synchronized execution
CA2309926A1 (en) * 1997-11-14 1999-05-27 Erik Muench Method for maintaining the synchronized execution in fault resilient/fault tolerant computer systems
US6230183B1 (en) 1998-03-11 2001-05-08 International Business Machines Corporation Method and apparatus for controlling the number of servers in a multisystem cluster
DE19814096B4 (de) 1998-03-30 2007-07-19 Abb Patent Gmbh Verfahren zur Umschaltung redundant geschalteter, gleichartiger Baugruppen
JP2000172624A (ja) * 1998-12-07 2000-06-23 Hitachi Ltd 入出力処理システム
GB2390442B (en) * 2002-03-19 2004-08-25 Sun Microsystems Inc Fault tolerant computer system

Also Published As

Publication number Publication date
DE50201568D1 (de) 2004-12-23
JP2004527829A (ja) 2004-09-09
ZA200304933B (en) 2004-04-23
EP1366416B1 (de) 2004-11-17
WO2002071223A1 (de) 2002-09-12
AU2002246102B2 (en) 2005-04-14
CN1488100A (zh) 2004-04-07
ATE282855T1 (de) 2004-12-15
RU2003129648A (ru) 2005-04-10
CN1262924C (zh) 2006-07-05
JP3867047B2 (ja) 2007-01-10
EP1366416A1 (de) 2003-12-03
EP1239369A1 (de) 2002-09-11
US20040158770A1 (en) 2004-08-12
RU2279707C2 (ru) 2006-07-10
US7260740B2 (en) 2007-08-21
ES2231677T3 (es) 2005-05-16
AU2002246102B9 (en) 2005-04-21

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