MXPA99007298A - Interrup control signal generator - Google Patents

Abstract

A scan frequency detector (208, 209) responds to a horizontal synchronization signal (HORZ-SYNC) to generate a data signal (208a) which is indicative of the horizontal scan frequency. A digital to analog (D / A) converter (201) produces, from the data signal, an analog output signal (60a) to a first level when the horizontal frequency is within a first scale of values, to a second level when the horizontal frequency is within a second scale of values, and at a third level when the horizontal frequency is within a third scale of values. A first switch (Q2) of a switched capacitor arrangement S (60) is turned on when the output signal is at a first level. The first switch (Q2) and a second switch (Q2i) of the switched capacitor arrangement S are turned on when the output signal is at a second level. Both the first and the second switches are turned off when the output signal is at a third level. The third and second Zener levels (Z

Description

SWITCH CONTROL SIGNAL GENERATOR FIELD OF THE INVENTION The invention relates to a switch control arrangement of a diverter circuit. For example, the switch control arrangement can be used to control switched S capacitor switches.

BACKGROUND OF THE INVENTION A television receiver, or a computer monitor, may have the ability to selectively display information in images on the same cathode ray tube (CRT) using a diverting current at different horizontal scanning frequencies. When the information is displayed in images of a television signal defined according to a broadcast standard, it may be more economical to use a horizontal deviating current at a speed of approximately 16 KHz, referred to as speed 1fH. Whereas when displaying information in images of a high-definition television signal or displaying a monitor data signal, the velocity of the horizontal deviating current may be equal to or greater than 32 KHz, referred to as 2nfH. The value of n is equal to or greater than 1. Typically, a capacitor S is coupled to a horizontal deviator winding of a horizontal deviator circuit output stage to correct a light beam arrival error related to the deviation referred to as correction S In a horizontal deviator circuit output stage of a visual display monitor capable of operating at multiple scanning speeds, it is known to vary the number of capacitors S in circuit using switched S capacitors. The selection of capacitors S is made through selectable switches, according to the selected horizontal deviation frequency. In a prior device, a microprocessor responds to a horizontal synchronization signal to generate a data signal containing a digital word that is determined by the selected horizontal frequency. The data signal is coupled to an input port of an integrated circuit (IC) that includes several digital to analog (D / A) converters. A given D / A converter can generate an output control signal that is coupled to the diverter circuit to adjust a diverter parameter, for example, the image width. The output control signals produced by the D / A converters are developed in output terminals separated from the IC. It may be desirable to use the D / A converters to generate switch control signals to select the capacitors S according to the horizontal frequency. It may be desirable to reduce the required number of D / A converters and the corresponding output terminals of the IC for a given number of capacitors S.

COMPENDIUM OF THE INVENTION To carry out an aspect of the invention, a given D / A converter generates an output signal having multiple levels or a number of selectable levels or states greater than two. For example, the output signal can be a three-level signal. The multilevel signal is coupled to control terminals of first and second capacitor switches S, advantageously by establishing three combining states of the capacitor S switches. In a display apparatus, by modeling an aspect of the invention, a synchronization signal It has a frequency selected from a scale of deviating frequencies. A diverter circuit responds to the synchronization signal to generate a diverting current in a diverter winding. A data signal source having a value that is indicative of the selected deviation frequency is generated. A digital-to-analog converter that responds to the data signal generates an output voltage analogous to a first level, when a first diverter frequency is selected, and to a second level, when a second diverter frequency is selected. A transistor switch responds to the output voltage of the digital-to-analog converter to selectively couple, in accordance with the first and second levels of the output voltage of the digital-to-analog converter, a capacitance S to the diverter circuit to provide the S correction. drawings: The only Figure illustrates a switched capacitor S control circuit, modeling one aspect of the invention.

DETAILED DESCRIPTION The only Figure illustrates a horizontal deviator circuit output stage 101 of a television receiver having multiple scanning frequency capability. Step 101 is activated by a regulated power supply 100 that generates a supply voltage B +. A conventional driving stage 103 responds to an input signal 107a at a selected horizontal scanning frequency, nfH. The driving stage 103 generates a drive control signal 103a to control the operation of the switch in a switch transistor 104 of the output stage 101. By way of example, a value of n = 1 may represent the horizontal frequency of a signal television according to a given standard, such as a broadcast standard. The collector of transistor 104 is coupled to a TOA terminal of a first winding T0W1 of a retraction transformer T0. The collector of transistor 104 is also coupled to a return capacitor 105. The collector of transistor 104 is further coupled to a horizontal deviating winding LY to form a back-resonant circuit. The collector of the transistor 104 is also coupled to a conventional damping diode 108. The winding LY is coupled in series with a linearity inductor LIN and a switched signal or capacitor S CS1. The capacitor CS1 is coupled between a terminal 25 and a reference potential, or ground GND, so that the terminal 25 is interposed between the inductor LIN and the capacitor S CS1. The output stage 101 is capable of producing a diverting current i and. The diverting current iy has substantially the same predetermined amplitude for any selected horizontal scanning frequency of the signal 103a, selected from a scale of 2fH to 2.4fH and for a selected horizontal frequency of 1fH. The control of the deviation current amplitude iy is achieved by automatically increasing the voltage B + the horizontal frequency is increased, and vice versa, in order to maintain a constant amplitude of the diverting current iy. The B + voltage is controlled through a conventional regulated power supply 100 which operates in a closed loop configuration through a feedback winding T0W2 of the transformer T0. The magnitude of the voltage B + is established, according to a feedback retraction pulse signal FB having a magnitude that is indicative of the current amplitude i and. A vertical velocity parabola signal, E-W, is generated in a conventional manner, not shown. The E-W signal is conventionally coupled to the power supply 100 to produce a vertical velocity parabola component of the B + voltage to provide the east-west pincushion distortion correction. A switch circuit 60 is used to correct an error of arrival of light beam, such as linearity. The circuit 60 selectively couples to none, only to one or both a signal capacitor CS2 and a signal capacitor CS3 in parallel with the signal capacitor CS1. The selective coupling is determined as a function of the frequency scale from which the horizontal scanning frequency is selected. In the switch circuit 60, the capacitor CS2 is coupled between a terminal 25 and a drain electrode of a field effect transistor (FET) switch Q2. A source electrode of transistor Q2 is coupled to ground GND. A protection resistor R2 which avoids excessive voltage through transistor Q2 is coupled through transistor Q2. A control signal 60a is generated in the digital to analog (D / A) converter 201. The control signal 60a is coupled through a voltage divider, which includes a resistor R7 and a resistor R6, to a base electrode of a threshold determination transistor Q3. An intermediate terminal 60c disposed between a resistor R3 and a resistor R4, forming an actuating voltage divider, is coupled to transistor collector Q3 and, through a resistor R4, to a gate electrode of transistor Q2. When the control signal 60a is large enough to turn on the transistor Q3, the gate voltage of the transistor Q2 is zero and the transistor Q2 is turned off. On the other hand, when the control signal 60a is not large enough to turn on the transistor Q3, the gate voltage of the transistor Q2 is activated by the voltage produced through the resistors R3 and R5 and the transistor Q2 is turned on. In the switch circuit 60, the capacitor CS3 is coupled between the terminal 25 and a drain electrode of a switch Q2 'of FET. The FET switch Q2 'is controlled by a control signal 60b in a similar way that the FET switch Q2 is controlled by a control signal 60a. In this manner, the resistors R3 ', R4' and R5 'and the transistor Q3' are coupled together and perform functions similar to the resistors R3, R4 and R5 and the transistor Q3, respectively. A control circuit 61, modeling an aspect of the invention, includes a microprocessor 208 that responds to a data signal 209a generated in a digital-to-analog signal converter 209. The signal 209a has a numerical value that is indicative of the frequency of a synchronization signal HORZ-SYNC or diverting current iy. The converter 209 includes, for example, a counter that counts the number of clock pulses, during a given period of the HORZ-SYNC signal and generates the word signal 209a according to the number of clock pulses occurring in the period dice. The microprocessor 208 generates a control data signal 208a which is coupled to an input of the D / A converter 201. The value of the signal 208a is determined in accordance with the horizontal speed of the HORZ-SYNC signal. The D / A converter 201 generates, in accordance with the data signal 208a, an analogous control signal 60a to an individual terminal 61a. The signal 60a is at a level that is determined by the signal 208a, according to the frequency of the HORZ-SYNC signal. Alternatively, the value of the signal 208a can be determined through a signal 209b that is provided through a keyboard, not shown. To carry out an aspect of the invention, the signal 60a is coupled through a threshold determination arrangement of a Zener diode Z1 coupled in series with the resistor R6 'to develop the switch control signal 60b in a terminal 61b . The signal 60b is developed between the diode Z1 and the resistor R6 '. Signal 60b is coupled to the base of transistor Q3 'through a base resistor R7'. As explained above, signal 60a controls transistor Q3, while signal 60b controls transistor Q3 '. When the frequency of the diverting current iy is 1fH, the signal TOa is at a minimum level of zero volts, so that the base voltage of the transistor Q3 does not exceed the forward voltage of the transistor Q3. Consequently, both transistors Q3 and Q3 'are turned off and transistors Q2 and Q2' are turned on. The result is that both capacitors CS2 and CS3 are coupled in parallel with the capacitor S not switched to establish a maximum value of capacitance S. When the frequency of the horizontal deviating current is equal to or greater than 2fH and less than 2.14fH, the signal 60a is at an intermediate level of 5V, so that the base voltage of transistor Q3 exceeds the forward voltage of transistor Q3. However, the level of the signal 60a does not exceed the voltage interruption of the Zener diode Z1. Consequently, transistor Q3 is turned on, transistor Q3 'is turned off, transistor Q2 is turned off and transistor Q2' is turned on. The result is that capacitor S CS2 is decoupled from capacitor S not switched CS1 and capacitor CS3 is coupled to capacitor S CS1 to establish an intermediate value of capacitance S. When the frequency of horizontal deviating current iy is equal to or greater than 2.14 fH, signal 60a is at a maximum level of 10V, so that the base voltage of transistor Q3 exceeds the forward voltage of transistor Q3. Also, the level of the signal 60a exceeds the voltage interruption of the Zener diode Z1 by an amount sufficient to produce a base voltage of the transistor Q3 'which exceeds the forward voltage of the transistor Q3'. Consequently, transistors Q3 and Q3 'are turned on and transistors Q2 and Q2' are turned off. The result is that the capacitors S CS2 and CS3 are decoupled from the non-switched capacitor S1 and establish a minimum value of capacitance S. Advantageously, the D / A converter 201 generates a multi-level output signal 60a having selectable levels or states. greater than two, that is, an output signal of three levels. Advantageously, the three-level signal establishes three selectable combination states of capacitor switch transistors S, Q2 and Q2 ', as follows: both transistors are turned off, both being turned on and only one of the transistors, transistor Q2, being switched on. Advantageously, the use of the D / A converter 201 to control the capacitor switch S simplifies the receiver control arrangement. This is because the D / A converter 201 can be included in an integrated circuit that includes other D / A converters, not shown. The other D / A converters can be used for other adjustment control functions, which do not require the switch operation. In this way, there is no need to treat the switch function of the S capacitors in a different way from the control functions without switch that provide adjustments.

Claims (7)

1. - A visual presentation apparatus, comprising: a synchronization signal source (HORZ-SYNC) having a selected frequency of a deviating frequency scale; a diverter circuit (101) responding to said synchronization signal to generate a diverting current (¡y) in a deviating winding (LY) and to generate a correction signal to correct an error of arrival of a light beam of a beam of electron light in a cathode ray tube; a source of a data signal (208a) having a value that is indicative of said selected diverting frequency; a digital-to-analog converter (201) that responds to said data signal to generate in a terminal (61a) an output signal (60a) having at least three selectable levels, wherein at a first level, a first level is selected deviating frequency, wherein at a second level, a second deviating frequency is selected and at a third level, a third deviating frequency is selected; and a plurality of switches (Q2, Q2 '), each responding to a given digital to analog output signal level, to selectively couple corresponding impedances (CS2, CS3) to said diverter circuit to establish said error correction signal of arrival of the light beam, according to a selected combination of states of the switches, so that the first, second and third combinations of states are selected according to the first, second and third levels, respectively, of the output signal (60a) of the digital to analog converter.

2. A visual display apparatus according to claim 1, further comprising a threshold detector (Z1) that responds to said output signal (60a) of the digital to analog converter to generate a first switch control signal in a control terminal of one of the switches that causes said switch to be in a first state, when said output signal of the digital-to-analog converter is in a first level, and in a second state when said output signal of the digital converter Analogue is in each of the second and third levels.

3. A visual display apparatus according to claim 2, wherein said threshold detector comprises a Zener diode (Z1).

4. A visual presentation apparatus according to claim 2, wherein said output signal (60a) of the digital-to-analog converter is coupled to a control terminal of the other of the switches (Q2, Q2 ') that causes the other switch is in said first state, when said output signal of the digital-to-analog converter is in each of the first and second levels, and in said second state, when said output signal of the digital-to-analog converter is to a third level.

5. A visual presentation apparatus according to claim 1, wherein said impedances comprise capacitances S (CS2, CS3).

6. A visual display apparatus according to claim 1, wherein said data signal source comprises a data-frequency converter (209) that responds to said synchronization signal (HORZ-SYNC).

7. A visual presentation apparatus, comprising: a synchronization signal source (HORZ-SYNC) having a selected frequency is a scale of deviating frequencies; a diverter circuit (101) responding to said synchronization signal to generate a diverting current (iy) in a diverter winding (LY); a source (208) of a data signal (208a) having a value that is indicative of said selected diverting frequency; a digital to analog converter (201) that responds to said data signal to generate an analog output voltage (60a) at a first level when a first deviation frequency is selected, and at a second level, when a second deviation frequency is selected; and a transistor switch (Q2, Q2 ') that responds to said output voltage (60a) of the digital-to-analog converter to selectively couple, in accordance with said first and second levels of the output voltage of the digital-to-analog converter, a capacitance S (CS2, CS3) to said diverter circuit (101) to provide the correction S.