MXPA99004719A - Method and apparatus for generating complex four-phase sequences for a cdma communication system - Google Patents

Abstract

An improved sequence design for code-division multiple access (CDMA) communications generating complex four-phase pseudo-random code sequences which may be directly mapped to a quadrature phase shift keying (QPSK) signal constellation.

Description

METHOD AND APPARATUS FOR GENERATING COMPLEX SEQUENCES OF FOUR PHASES FOR A CDMA COMMUNICATION SYSTEM BACKGROUND OF THE INVENTION Field of the Invention The present invention relates generally to an improved sequence design for code division multiple access (CDMA) communications. More particularly, the invention is directed to generate pseudorandom code sequences of four complex phases which can be mapped directly to a quadrature phase shift commutation signal (QPSK) constellation.

Description of the prior art Code division multiple access (CDMA) is a type of spread spectrum communication system where each subscriber unit differs from all other subscriber units by the position of a unique code. In order to communicate with a particular subscriber unit, a transmitting unit prints the unique code on a transmission and the receiving unit uses the code to decode the transmission. CDMA communication systems transmit Voice and data information using signals that appear similar to noise and random. Since the random sequences are generated by standard deterministic logic elements, the generation of the bit sequences is predictable and repeatable. It is the use of these repeatable binary random sequences that allows the phase and modulation of any digital signal that conveys information for data communications. These predictable random sequences are called pseudorandom sequences. Each subscriber unit in a CDMA communication system receives a plurality of pseudorandom sequences from base stations which are within the communication range of the subscriber unit. As indicated above, the receiving unit uses a particular pseudo-random code to try to decode one of the received pseudo-random sequences. The particular code can only be used to decode a pseudorandom sequence, the other pseudo-random sequences received contribute to the noise. As the correlation between the pseudorandom sequences used by the CDMA communication system decreases, the amount of noise output by the receiving unit also decreases. This decrease can be explained as follows: there is a high correlation between a pseudo-random sequence that includes the data that will be transmitted to the unit subscriber and the pseudorandom sequence generated by the receiver. As the correlation between a pseudo-random sequence and the other pseudo-random sequences (ie, cross-correlation) decreases, it becomes easier for the subscriber unit to recognize its particular pseudo-random sequence and to filter all of the other pseudo-random sequences. Therefore, the noise is reduced and the clarity of the signal is improved. There is a need for an improved pseudorandom sequence generator which generates sequences having improved cross-correlation properties to reduce the noise experienced by the receiver. There is also a need for a pseudorandom code generator that is easy to implement.

BRIEF DESCRIPTION OF THE INVENTION The present invention provides an improved method and apparatus for generating pseudorandom code sequences of four complex phases, which can be easily mapped to a QPSK signal constellation and which have a low cross-correlation and a low-level autocorrelation. In one embodiment, a pseudo-random code generator produces four-phase CDMA codes with complexes using an accumulator and a plurality of tilters. The accumulator receives a quotient of a parameter M divided by a parameter N and receives feedback from a plurality of tilters. The parameters M and N are integers, where M is relatively prime with respect to N. The accumulator suits the quotient with the data received from the tilters and transmits the combined data to the tilters.

Two bits are extracted and used to produce the I and Q codes. In another embodiment, a pseudorandom code generator produces CDMA codes of four complex phases by providing a circuit to transmit an arithmetic progression of values and an incremental value of the progression arithmetic of values. The pseudorandom code generator also contains a first mixer to receive the arithmetic progression of values and incremental values. A second mixer receives the output of the first mixer and combines this output with the quotient of a parameter 2M divided by the parameter N, where M and N are integers and M is relatively prime with respect to N. Two bits are extracted from the second mixer and it becomes I and Q codes. Other advantages will become apparent to those familiar with the art upon reading the detailed description of the preferred embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a spread spectrum transmitter of the present invention; Figure 2 is a block diagram of a spread spectrum receiver of the present invention; Figure 3 is a timing diagram of a conventional pseudorandom code sequence; Figure 4 is a first embodiment of a spread spectrum code generator for generating four phase sequences according to the present invention; Figure 5 is a diagram showing the conversion to I and Q in the first mode of the spread spectrum code generator; Figure 6 is a diagram showing the method steps for generating four phase sequences according to the first embodiment of the present invention; Figure 7 is a second embodiment of a spread spectrum code generator for generating four phase sequences according to the present invention; Figure 8 is a diagram showing the conversion to I and Q in the second mode of the spread spectrum code generator; Figure 9 is a diagram showing the method steps for generating four phase sequences according to the second embodiment of the present invention; Figure 10 is a graph of an example of an autocorrelation function for the first suboptimal implementation. Figure 11 is an example of a cross-correlation function for the first suboptimal implementation.

DESCRIPTION OF THE PREFERRED MODALITIES Preferred embodiments are described with reference to the figures of the drawings in which similar numbers represent similar elements therethrough. A spread spectrum transmitter 10, as shown in Figure 1, includes an analog-to-digital (A / D) converter 12 for receiving a speech signal. A switch 14 receives both the digital voice signal from the A / D converter 12 and a digital data signal from a terminal (not shown). The switch 14 connects the spread spectrum transmitter 10 with an input for the digital voice signal or the digital data. The digital voice signal and the digital data are subsequently collectively referred to as digital data. The switch 14 directs the digital data to a spreader or separator 20, which may comprise a mixer. A sequence is applied pseudorandom generated by the code generator 30 to the spreader 20. The code generator 30 and the spreader 20 are shown contained within the spread spectrum encoder 40. The disseminator 20 performs a frequency spectrum dissemination function by multiplying the digital data by the pseudo-random sequence in a time domain, which is equivalent to performing a convolution of the bimodal spectrum of the digital data with the approximately rectangular spectrum of the sequence pseudo-random in the frequency domain. The output of the spreader 20 is applied to a low pass filter 50, whose cutoff frequency is equal to the system chip rate, Fcr. The output of the low pass filter 50 is then applied to a terminal of a mixer 60 and is subjected to upconversion, determined by the carrier frequency Fc which is applied to the other terminal. The signal subjected to upconversion then passes through a bandpass filter 70, which may be a helical resonator. The filter 70 has a bandwidth equal to twice the chip rate and a center frequency equal to the center frequency of the bandwidth of the spread spectrum system. The output of the filter 70 is applied to the input of an RF amplifier 80, whose output activates an antenna 90. In Figure 2 a receiver 100 of spread spectrum is shown. An antenna 110 receives the spread spectrum signal transmitted which is filtered by a bandpass filter 120. The filter has a bandwidth equal to twice the chip rate Fcr, and a center frequency equal to the center frequency bandwidth of the spread spectrum system. The output of the filter 120 is further down-converted by a mixer 130, possibly in two stages, to a baseband signal using a local oscillator having a constant frequency which is approximately the same as the carrier frequency Fc of the transmitter 10. Subsequently, the output of the mixer 130 is disseminated (dissemination is eliminated) by applying it to the first terminal of the disseminator 140 while applying the same pseudo-random sequence as that provided to the disseminator 20 to a second terminal of the disseminator 140. The pseudo-random sequence is generated by a code generator 30. The spreader 140 and the code generator 30 are contained within a spread spectrum decoder 160, as shown in Figure 2. The output of the spreader 140 is applied to a low pass filter 180, which has a cutoff frequency. at the data rate of the data input to the spread spectrum transmitter 10. The output of the low pass filter 180 is a replica of the data input to figure 1. It should be appreciated by those familiar with the art that the pseudo-random sequence used in the receiver 100 of a spread spectrum communication system should be synchronized with the pseudo-random sequence used in the transmitter 10. Methods for obtaining this synchronization are also well known. A conventional dissemination sequence is a pseudo-random digital sequence as shown in Figure 3. The sequence is used to disseminate the signal that is transmitted and to dis-disseminate the signal that is received. Two different binary codes using two different LFSR circuits provide I and Q channels for data transmission. However, if there is a high cross-correlation between channels I and Q on the receiver side, a large amount of noise will be transmitted by the receiver. The code generator 30 of the present invention generates pseudo-random code sequences with greatly improved cross-correlation properties compared to prior-art pseudorandom sequences such as one shown in FIG. 3. A pseudo-random sequence of the prior art essentially comprises a signal that has different frequency components. This signal is a combination of the sinusoidal waveforms that have different sequences: • both high-frequency sinusoidal waveforms and low-frequency sinusoidal waveforms. Therefore, the signal has a frequency spectrum which can be divided into frequency regions. Those sinusoids that have the strongest frequencies (greater amplitudes) will be more dominant in the signal that those sinusoids that have weaker frequencies (smaller amplitudes). However, in order to generate an improved pseudo-random code (a highly random code) as in the present invention, the amplitude force in each frequency region may be the same. Highly random codes have the property that they contain components in all frequency regions, resulting in a flat spectrum. The code generator 30 generates a pseudo-random sequence in which the amplitude of the sinusoids in all frequency regions is approximately the same (flat), as will be explained in detail in the following. A pseudo-random sequence having a length N and frequency X regions can be represented by Y frequency binary expressions of a discrete Fourier series representation, wherein each frequency region corresponds to a frequency region. There exist Y binary expressions for the X regions of frequency (2tr / T) k, k = 0, ..., N-l where T is the period of the sequence of dissemination in time, and X = Y = N. The instantaneous frequency of the sequence ideally spends an equal time in each of the regions of frequency X. Therefore, each frequency region will have the same force. For example, suppose that s (t) indicates the sequence of dissemination which is periodic, then s (t) = S ckej2pkt / t Equation (1) k is the representation of the Fourier series where ck = 1 Sts (t) e-j2"kt / tdt Equation (2) T where ck is the strength of the sinusoids in one of the discrete Fourier series representations or the strength of the sinusoids in the frequency region or region. The average power in s (t) is written as follows: P =? | Ck | 2 Equation (3) k The magnitude spectrum of s (t) is | ck | and the power spectrum is | ck | 2. The ideal power spectrum is flat, where the average power is distributed over all frequency regions equally. This results in a close autocorrelation. The whole of | ck | 2 must be equal. To obtain this, the instantaneous frequency is: *? Mk, k = 0, ..., N-l Equation 4 where M and N are integers and M is relatively prime with respect to N (M and N do not have the same common factor). This guarantees that each frequency region (2p / T) k is visited equally. For example, if N = 7 and M = 3, the instantaneous frequency is then 0, 2p x3 2tr x6, 2p xl? Equation (5) Since a discontinuity in the phase has the effect of spreading the power in other frequency regions, the phase is preferably continuous and free of sudden jumps as much as possible. The main restriction is that the phase of the complex dissemination sequence can be limited to. { 0, tt / 2, p, 3tr / 2} . This limitation leads to sudden phase changes and prevents the power spectrum from becoming completely flat. However, a sequence with a relatively flat power spectral density can be obtained. For the phase to be continuous at t = (k / N) T, the recursive equation is ? k-1-? k = 2JG Mk Equation 6 N where ? it is the individual chip phase in a sequence and k is the index (order) of the chips in the sequence. If? 0, is chosen as one of (0, p / 2, p, 3p / 2), then Q1,? 2, ..., TN can be generated sequentially. This solution results in a flat spectrum, which is the optimal solution. The choice of? 0 (0, p / 2, 7T, 3p / 2) does not produce differences due to a constant phase shift on the spectral properties. The suboptimal implementation of the above equation when? K is limited to. { 0, 7r / 2, p, 3p / 2) is as follows: ?? -? -? = p (| _4 mod4) Equation (7) 2 N where | _4 (M / N) kJ means the largest whole number less than or equal to 4 (M / N) k. This equation is a modified version of Equation (6) and performs the mapping of phase angles to one of four points for QPSK implementation. Limit the phases to the set. { 0, p / 2, p, 3p / 2} . As the phase sequential deviation continues to develop a second suboptimal implementation, one has: Equation (8) 2ttMk-lt_ pMkt? * = T N T N Equation (9) Again, the second suboptimal implementation with four phases (0, p / 2, p, 3p / 2) is obtained as: ? k =? 0-p (l_2Mk (k + l) _ | mod4 Equation (10) 2 N If? 0 = 0, then: = p L2Mk (k + l) J mod4 Equation (11) 2 N for this second suboptimal implementation. In examining Equation 6, one observes that each phase term can be obtained by adding a variable term (2 p / N (Mk) to the previous phase.) Moreover, since 2pk is equal to zero the 2p module, the term one needs Adding in each phase to find the next phase is reduced to (M / N), which is not an integer, so a possible implementation can be a recursive additive (accumulator) which adds the term (M / N) ) to the phase in each interaction Figure 4 shows a first mode of the code generator 30 for generating four-phase pseudo-random code sequences which greatly improve the autocorrelation properties and the cross-correlation properties. An example of the first suboptimal implementation of equation 7. Although four-phase sequences of any length can be generated, a length of 127 bits is selected as an example. In this example, there is a number N of chips in a symbol, which represents the processing gain. You select a number M which is relatively prime with respect to N, which means that M and N do not have a common factor. The number of L bits necessary to provide a binary representation of the processing gain N is determined by solving the following equation: N = 2L. Equation (12) The code generator 30 includes an accumulator 31 which has a length of 2L bits. Since N = 127 in this example, L = 8. Therefore, the accumulator 31 has a length of 16 bits. An eighth bit M / N number is applied to the inlet of the accumulator 31. A number of sixteen bits of the tilter 32i to 322L is applied to a second input for the accumulator 31. The tilters 32x to 322L can be replaced by a record of displacement. Although the bits are input to the rockers 323, -323 !, and the parallel accumulator 31, the bits can also be entered in series. The sum of the two numbers entered in the accumulator 31 is transmitted to the tillers 32x to 322L. An extractor 33 extracts the fifth and sixth less significant bits of the 32x to 322L joggers (see Figure 5). The fifth and sixth least significant bits are applied to an exclusive gate or (or) 34. The output of gate 34 or excluder is converted to a value Q by a converter 36. The output of the sixth bit of the the extractor 33 is converted to an I value and by the converter 35. The output of the I and Q values of the converters 35 and 36 is applied to the spreader 20 or spreader 140. As indicated above, M / N is an eighth number of bit in this example. The fifth and sixth bits of the accumulator output represent the first two significant bits of 4 (M / N) which appear in Equation (7). When 4 (M / N) is mapped to one of four values. { 0, 1, 2, 3.}. by taking module 4, the result is the first two significant bits of 4 (M / N), or the fifth and sixth equivalent bits of the accumulator. Figure 6 shows a flow chart of the method performed by the circuit shown in Figure 4. The initial parameters M and N are loaded into the registers or memory (not shown) before performing the division function (M divided by N). ). In addition, the value in the accumulator 31 is preferably equal to zero. The remaining apparatus in the code generator 30 is also initialized (YES). The sum, which is initially zero, is added to the M / N ratio (S2). The fifth and sixth bits of the new sum are extracted (S3) in order to be converted into I and Q values (S4 and S5). The bits (L-2) and (L-3) must be mapped to the constellation QPSK as follows: OO? Ll Ol? L-l 10? -1-1 ll? -ll This mapping can be done in software or hardware by first using: and then using the standard mapping O? l, l? -l. For example, if the sixth bit for L-2 bit is equal to zero, then the value I is one. If the sixth bit is a one, then the value I is a negative one. In the case of the Q value, if the output of gate 34 or excluder is a zero, the value of Q is one. If the output of gate 34 or excluder is a one, the value Q is a negative one. The I and Q values are transmitted to the disseminator 20 or spreader 140 (S6). The method steps S2 to S6 are repeated until all the digital data supplied by the switch 14 is transmitted or all the data is received by the switch 190. Figure 7 shows a second mode of a code generator 200. The code generator 200 is replaced by the code generator 30 and generates pseudo-random code sequences of four phases similar to those generated by the code generator 200 which greatly improves the autocorrelation properties and the cross-correlation properties. The second mode is an example of the second suboptimal implementation of equation (11). Although four-phase sequences of any length can be generated, a length of 127 bits is selected as an example. further, for the purposes of this example, there are N numbers of chips in a symbol which represent the processing gain. A number M which is relatively prime relative to N is selected. The number of L bits required to provide a binary representation of processing gain N is determined by solving equation (12). Since M = 127 in this example, L = 8. Therefore (M / N) is sixteen bits in length. The code generator 30 includes an accumulator 210 which is L bits in length. The accumulator 210 has a length of 8 bits. A "1" is preferably applied to an inlet of the accumulator 210. The number of tilters 220x to 220L is applied to a second inlet of the accumulator 210. The tilters 220! at 220t can be replaced by a shift register. Although the bits are input to flip-flops 220-L to 220L, and to the accumulator 210 in parallel, the bits can be input in series. The sum of the entry of two numbers in the accumulator 210 is transmitted to the tillers 220- ,. to 220L. The output of the tillers 220x to 220L is transmitted to tilters 230x to 230L, as well as to the mixer 240. The mixer 240 also receives the output of the tilters 230x to 230L. The accumulator 210 and the tilters 2203.-220 ^, the tilters 230 ^ 230L and the mixer 240 provide the jog feedback circuit. The output of the mixer 240 is input to the mixer 250. The mixer 250 also receives an 8-bit input from (M / N). The extractor 260 extracts the less significant fifth and sixth bits of the mixer 250. The less significant sixth bit transmitted from the extractor 260 is converted to an I value by the converter 280. The fifth and sixth least significant bits are applied to a gate 270 or excluding. The output of the gate 270 or excluder is converted to a value Q by a converter 290 as shown in FIG. 8. The I and Q values transmitted from the converters 280 and 290 are applied to the disseminator 20 or desymerminator 140. As indicated before, (M / N) is an eighth bit number in this example. The tilters 220x to 220L transmit a value k and the tilters 230-L to 230L transmit the value k + 1 to the mixer 240. The mixer 250 receives the output of the mixer 240 and the product of (M / N). When mapping 2 (M / N) k (k + 1) to one of the four values. { 0, 1, 2, 3.}. when taking the module 4, the result is the fifth and sixth bits of the extractor 260 (see figure 8). Figure 9 is a flow chart of a method performed by the circuit shown in Figure 7. The parameters initials M and N are loaded in registers or in memory (not shown) before performing the division function (M / N). In addition, the value k is preferably equal to zero. The remaining apparatus in the second mode of the code generator 200 is also initialized (SI). The value (M / N) k (k + 1) (S2) is calculated. The fifth and sixth bits resulting from the above calculation are extracted (S3) in order to convert them into I and Q values (S4 and S5). The bits (L-2) and (L-3) must be mapped for the QPSK constellation as follows: OO? Ll Ol? Ll ao? -ii ll? -ll This mapping can be done in software or hardware by first using : and then using the standard mapping O? l, l? -l For example, if the sixth bit for L-2 bit is equal to zero, then the value I is one. If the sixth bit is a one, then the value I is a negative one. In the case of the Q value, if the output of gate 270 or excluder is a zero, the value of Q is one. If the output of gate 270 or excluder is a one, the value Q is a negative one. The I and Q values are transmitted to the disseminator 20 or spreader 140 (S6). The value k increases. Method steps S2 to S7 are repeated in all digital data supplied by switch 14 and transmitted when all data is received by switch 190. Figure 10 shows a portion of "autocorrelation where N = 127 and M = 44, which is the result of using the first suboptimal implementation to generate the pseudo-random code, Figure 11 shows a cross-correlation function where N = 127 and M = 44, which is the result of using the first suboptimal implementation for generate the pseudorandom code The autocorrelation a (n) for the sequence s (k) is given as: a (n) = s (k) s * (k + n) k = l Equation (13) where the indexes in parentheses are the module N taken and the cross-correlation c (n) of the two sequences s (k) and r (k) is given as: c (n) =? s (k) r * (k + n) k = l Equation (14) where again the index is the module N taken. The first suboptimal implementation achieves the desirable result of making the magnitude of the cross-correlation and the autocorrelation (except for a (0)) small compared to N. Although the results of the second suboptimal implementation example are not shown, the results are similar. Equations 13 and 14 are well known to those usually familiar in the art. Although the invention has been described in part by making a detailed reference to certain specific embodiments, it is intended that such detail be instructive rather than restrictive. It will be appreciated by those familiar with the art that many variations in the structure and mode of operation can be made without departing from the spirit and scope of the invention as described in the teachings herein.

Claims (19)

1. An apparatus for generating complex, four-stage code division multiple access codes (CDMA), characterized in that it comprises: a plurality of tillers, which initially adjust to zero; an accumulator having a first input to receive an output from the plurality of tilters and a second input to receive a quotient of a parameter M divided by a parameter N, where M and N are integers and where M is relatively first respect to N; the accumulator combines data received via the first and second inputs and transmits the combined data to the tilters; an extractor extracts the first bit and the second bit from the joggers; and a means for converting the first bit and the second bit to the I and Q code.

2. The apparatus according to claim 1, characterized in that the plurality of tillers provides a feedback and the accumulator is an addition.

3. The apparatus according to claim 1, characterized in that there are sixteen tilters that progressively represent more specific bits, the first extracted bit is the fifth least significant bit, and wherein the second extracted bit is the sixth least significant bit.

4. The apparatus according to claim 1, characterized in that the I and Q code is transmitted to a spreader or separator.

5. The apparatus according to claim 1, characterized in that the I and Q code is transmitted to a desymerminator.

6. A method for generating complex, four-stage code division multiple access (CDMA) codes, characterized in that it comprises: (a) providing a register having a plurality of bits initially set to zero; (b) selecting a first parameter M and a second parameter N where M and N are integers and M is relatively prime with respect to N; (c) combining the M / N quotient with the content of the register to produce a combination of bits; (d) replace the content of the record with the combination of bits; (e) extract the first and second bits of the record; (f) generating the I and Q code of the first and second extracted bits; (g) transmit the I and Q code; and (h) repeating steps (c) to (g).

7. The method according to claim 6, characterized in that the register has sixteen bits of progressively greater significance and the first bit is the fifth least significant bit of the sum, and wherein the second bit is the sixth least significant bit of the sum.

8. The method according to claim 6, characterized in that the combination is performed by an adder which transmits the sum of the M / N quotient and the content of the register.

9. The method according to claim 6, characterized in that the I and Q code is transmitted to a spreader.

10. The method according to claim 6, characterized in that the I and Q code is transmitted to a desymerminator.

11. An apparatus for generating code division multiple access codes (CDMA) of four complex phases, characterized in that it comprises: means for transmitting an arithmetic progression of values; a means to transmit an incremental value of the arithmetic progression of values; a first mixer having a first input to receive the arithmetic progression of values and a second input to receive the incremental values; a second mixer having a joint input that receives an output from the first mixer and a second input that receives the quotient of a parameter M divided by a parameter N, where M and N are integers and where M is relatively prime with respect to N; an extractor associated with the output of the second mixer for extracting a first bit and a second bit from the second mixer; and a means for converting the first and second extracted bits to code I and Q.

12. The apparatus according to claim 10, characterized in that the means for transmitting an arithmetic progression of values and the means for transmitting an incremental value of the arithmetic progression of values includes at least one shift register.

13. The apparatus according to claim 10, characterized in that the first bit is the fifth least significant bit of the second mixer, and the second bit is the sixth least significant bit of the second mixer.

14. The apparatus according to claim 10, characterized in that the I and Q codes are transmitted to a spreader.

15. The apparatus according to claim 10, characterized in that the I and Q codes are transmitted to a desymerminator.

16. A method for generating four-phase code division multiple access codes (CDMA), characterized in that it comprises: (a) selecting an M parameter and a processing N gain, where M and N are integers and M is relatively prime with respect to N; (b) dividing a processing gain N between M to provide a quotient; (c) mixing the quotient with an arithmetic progression of values and an incremental value of the arithmetic progression of values to provide a result; (d) extract the first and second bits of the result; (e) generating I and Q data of the first and second extracted bits; (f) transmit the I and Q data; and (g) repeating steps (c) to (f).

17. The method according to claim 15, characterized in that the first bit is the fifth least significant bit of the mixer, and wherein the second bit is the sixth least significant bit of the mixer.

18. The method according to claim 15, characterized in that the data I and Q are transmitted to a disseminator.

19. The method according to claim 15, characterized in that the data I and Q are transmitted to a desymerminator.