MXPA99003948A - Method and apparatus for decoding variable rate data - Google Patents

Abstract

A system and method for determining the data rate of a frame of data at a receiver (50) of a variable rate communications system. A vocoder at a transmitter encodes a frame of data at one of the rates of a predetermined set of rates. The data rate is dependent on the speech activity during the time frame of the data. The data frame is also formatted with overhead bits, including bits for error detection and detection. At the receiver (50), the data rate for the frame is determined based on hypothesis testing. Because the data rate is based on speech activity, a hypothesis test may be designed based on the statistics of speech activity. The received data frame is first decoded by a decoder (34) into information bits at the most probable rate as provided by the hypothesis testing module (36). Data check element (42) generates error metrics for the decoded information bits. If the error metrics indicate that the information bits are of good quality, then the information bits are presented to a vocoder (44) at the receiver to be processed for interface with the user. If the error metrics indicate that the information bits have not been properly decoded, then decoder (34) decodes the received data frame at the other rates of the set of rates until the actual data rate is determined.

Description

METHOD AND DEVICE FOR DECODING VARIABLE SPEED DATA BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital communications. More particularly, the present invention relates to a novel and improved system and method for determining, at a receiver of a variable speed communication system, the speed at which the data has been encoded for transmission. 2. Description of Related Art The use of code division multiple access modulation (CDMA) techniques is one of several techniques for facilitating communications, in which a large number of users of the system are present. Although other techniques are known, such as multiple time division access schemes (TDMA), frequency division multiple access (FDMA), and AM modulation, such as the single compressed-extended amplitude sideband (ACSSB) , the CDMA has significant advantages over these other techniques. The use of CDMA techniques in a multiple access communication system is described in U.S. Patent No. 4,901,307, entitled "MULTIPLE ACCESS COMMUNICATION SYSTEM OF EXTENDED SPECTRUM USING SATELLITE OR TERRESTRIAL REPEATER", granted to the beneficiary of this invention and incorporated here as a reference. CDMA systems often employ a variable speed vocoder to encode data, so that the data rate can be varied from one data block to another. An exemplary embodiment of a variable speed vocoder is described in U.S. Patent No. 5, 414, 196, entitled "VARIABLE SPEED VOCODER", issued to the beneficiary of the present invention and incorporated herein by reference. The use of a variable speed communications channel reduces mutual interference by eliminating unnecessary transmissions when it is not useful to transmit voice. Algorithms are used within the vocoder to generate a variable number of bits of information in each block, according to the variations in vocal activity. For example, a vocoder with a four-speed set can produce data blocks of 20 milliseconds, which contain 16, 40, 80 or 171 bits of information, depending on the activity of the speaker. It is desired to transmit each block of data in a fixed period of time, varying the transmission speed of the communications. Further details on the format of vocoder data in data blocks are described in U.S. Patent No. 5,511,073, entitled "METHOD AND DEVICE FOR GIVING DATA FORMAT FOR TRANSMISSION", granted to the beneficiary of the present invention and incorporated herein. as reference. The data blocks can be additionally processed, modulated by extended spectrum, and transmitted as described in U.S. Patent No. 5,103,459, entitled "SYSTEM AND METHOD FOR GENERATING WAVE FORMS IN A CDMA CELLULAR TELEPHONE SYSTEM", granted to the beneficiary of the present invention and incorporated herein by reference. Variable speed systems can be developed, which include explicit speed information. If the speed is included as part of a variable speed block, then the speed is not recoverable until after the block has already been properly decoded, at which point the speed has already been determined. Instead of including the speed in a variable speed block, the speed could instead be sent in a non-variable speed portion of the block. However, typically only a few bits are needed to represent the speed, and those bits can not be efficiently coded and interleaved to provide protection against errors by fading communication channels. In addition, the speed information is only available after some decoding delay and is subject to errors. Alternatively, variable speed systems can be developed, which do not include explicit speed information. One technique for the receiver to determine the speed of a received data block, wherein speed information is not explicitly included in the block, is described in co-pending US Patent Application Serial No. 08 / 233,570, entitled "METHOD AND DEVICE FOR DETERMINING THE SPEED OF DATA, OF VARIABLE SPEED DATA TRANSMITTED IN A COMMUNICATIONS RECEIVER", filed on April 26, 1994, granted to the beneficiary of the present invention, and incorporated herein by reference. Another technique is described in co-pending US Patent Application Serial No. 08 / 126,477, entitled "MULTIPLE SPEED SERIES VITERBI DECODER FOR APPLICATIONS TO MULTIPLE ACCESS SYSTEMS BY CODE DIVISION", filed September 22, 1993 , granted to the beneficiary of the present invention, and incorporated herein by reference. According to these techniques, each block of data received is decoded in each of the possible speeds. The error metric, which describes the quality of the decoded symbols for each block decoded at each speed, is provided by a processor. The error metric can include the results of the Cyclic Redundancy Verification (CRC), Yamamoto Quality Metrics, and Symbol Error Percentages. These error metrics are well known in communication systems. The processor analyzes the error metrics and determines the most probable speed at which the incoming symbols were transmitted. Decoding each block of data received at each possible data rate, would eventually generate the desired decoded data. However, searching through all possible speeds is not the most efficient use of processing resources in a receiver. Also, when higher transmission speeds are used, the power consumption to determine the transmission speed also increases. This is because there are more bits per block that have to be processed. In addition, as technology evolves, variable-speed systems could use larger sets of data speeds to communicate information. The use of large sets of speeds will make the decoding exhaustive at all possible speeds impossible. In addition, the encoding delay will not be tolerable for some system applications. Consequently, a more efficient speed determination system is required in a variable speed communications environment. These problems and deficiencies are clearly understood in the art and are solved by the present invention, in the manner described below.

BRIEF DESCRIPTION OF THE INVENTION The present invention is a novel and improved method and system for determining the communication transmission speed in a variable speed communication system. In a variable speed system, the data rate at which a data block is encoded can be based on the vocal activity during the time interval. Because the characteristics of the voice are known, functions can probably be defined for the data rates that depend on the characteristics of the voice. The probability functions may, in addition, depend on the measured statistics of the data blocks received. In addition, hypothesis tests based on probability functions can be designed to determine the most likely data rate of a received data block. These probability functions may depend on the selected service option. For example, the probability functions for data services will be different from those for voice services. In the receiver of the present invention, a processor causes a decoder to decode the received data block into information bits at the most probable speed, as determined by the hypothesis test. The most likely speed may, for example, be the speed of the previous data block. The decoder also generates error metrics for the decoded information bits. The bits decoded in the error metrics are provided to a data verifier element, which verifies the bits decoded for correction. If the error metrics indicate that the decoded information bits are bits of good quality, then the information bits are provided to a vocoder, which further processes the data and provides the user with voice. Otherwise, a fault signal is presented to the processor. The processor then causes the decoder to decode the received data block at the other data rates, until the correct data rate is found.

BRIEF DESCRIPTION OF THE DRAWINGS The characteristics, objects and advantages of the present invention will be more evident from the detailed description set forth below, when taken in conjunction with the drawings, in which similar reference characters are identified in a manner corresponding to all along these and where: FIGURE 1 is a schematic overview of an exemplary CDMA cellular telephone system; FIGURE 2 is a block diagram of a variable speed receiver system with particular reference to the speed determining features of the present invention; > FIGURES 3 and 4 are flow diagrams illustrating two embodiments of the processing steps involved in speed determination, where the hypothesis test designates the speed of the previous data block, as the most probable speed for the block of data. current data; FIGURES 5 and 6 are flow charts illustrating two modes of the processing steps involved in speed determination, where the hypothesis test was based on the a priori probability distribution of the data rates; and FIGURES 7 and 8 are flowcharts illustrating two embodiments of the processing steps involved in speed determination, where the hypothesis test was based on the conditional probability distribution of the data rates.

DETAILED DESCRIPTION OF THE PREFERRED MODALITIES An exemplary mobile cellular telephone system, in which the present invention is incorporated, is illustrated in FIGURE 1. For purposes of the example, this system is described herein within the context of a CDMA cellular communication system . However, it should be understood that the invention is applicable to other types of communication systems, such as personal communication systems (PCS), wireless local circuit, subscriber switch board (PBX) or other known systems. In addition, systems using other well-known transmission modulation schemes, such as TDMA and FDMA, as well as other spread spectrum systems, can employ the present invention. An exemplary cellular system, in which the speed determination system of the present invention can be implemented, is illustrated in FIGURE 1. In FIGURE 1, the controller and switch 10 of the system typically include the interface and physical components of the system. appropriate processing to provide system control information to cell-sites. The controller 10 controls the routing of telephone calls from the public switched telephone network (PSTN) to the appropriate cell-site, for transmission to the appropriate mobile unit. The controller 10 also controls the routing of calls of the mobile units via at least one cell-site to the PSTN. The controller 10 can direct calls between the mobile users via the appropriate cell-site stations, since such mobile units typically do not communicate directly with each other. The controller 10 can be coupled to the cell-sites by various means, such as dedicated telephone lines, fiber optic links or radio frequency communications. In FIGURE 1, two example cells-sites 12 and 14 are illustrated, along with two exemplary mobile units, 16 and 18, which includes cell phones. Arrows 20a-20b and 22a-22b respectively define the possible communication links between cell-site 12 and mobile units 16 and 18. Similarly, arrows 24a-24b and arrows 26a-26b, respectively, define the possible communication links between the cell-site 14 and the mobile units 18 and 16. The cellular system illustrated in FIGURE 1, can employ a variable-speed data channel for communications between cell-sites 12, 14 and the mobile units 16, 18. For example, a vocoder (not shown) can encode speech information sampled in symbols at four different speeds, in accordance with the IS-95-A standard. The Compatibility Standard Mobile Station IS-95-A Base Station for Dual-Mode Extended Broadband Spectrum Cell Systems has been provided by the Telecommunications Industry Association (TIA) for CDMA communications. According to IS-95-A, the voice is coded at approximately 8.550 bits per second (bps), 4,000 bps, 2,000 bps, and 800 bps, based on vocal activity during a data block of 20 milliseconds (ms) . Each vocoder data block is then formatted with supplementary bits, data blocks of 9,600 bps, 4,800 bps, 2,400 bps, and 1,200 bps for transmission. The block of 9, 600 bps is known as a full speed block; the 4,800 bps data block is known as a half-speed block; and a 2,400 bps data block is known as a quarter-speed block; and a data block of 1,200 bps is known as a one-eighth speed block. Although this example describes a set of four data rates of the IS-95-A standard, it should be recognized that the present invention is equally applicable in systems using different transmission speeds and / or a different number of variable speeds. By coding each block of data based on vocal activity, data compression is achievable without having an impact on the quality of the reconstructed voice. Since the voice inherently contains periods of silence, ie pauses, the amount of data used to represent those periods can be reduced. Variable speed vocoding exploits this fact more effectively, reducing the data rate for those periods of silence. In a system with a set of four speeds as described above, periods of active voice will generally be coded at full speed, while periods of silence will generally be coded at one-eighth speed. Most blocks (approximately 80-90%) are encoded at full speed or at an eighth speed. Transitions between the active voice and periods of silence will typically be coded to a half or quarter of a speed. An exemplary coding technique, which compresses data based on vocal activity is described in U.S. Patent No. 5,511,073, mentioned above. The data blocks are also formatted with supplementary bits, which will generally include additional bits for correction and error detection, such as the Cyclic Redundancy Verification (CRC) bits. The CRC bits can be used by the decoder to determine whether or not a block of data has been correctly received. The CRC codes are produced by dividing the data block by a predetermined binary polynomial, as described in detail in IS-95-A. In a preferred embodiment, each symbol data block is interleaved by an interleaver, preferably based on the bit level, to increase the time diversity for error detection purposes. The formatted data blocks undergo additional processing, which includes modulation, up-conversion by frequency to the radio frequency (RF) and amplification of the signals of the data blocks, before transmission. When the signals of the variable speed data blocks are received by a receiver, the receiver must determine the transmission speed in order to decode the signals appropriately. However, the speed of the block received is not known by the mobile station a priori. Therefore, some other method is necessary to determine the speed. The present invention effects the determination of the speed through the use of hypothesis tests. The hypothesis tests were designed based on the probability distribution of the data rates of the speech blocks. Although the data rate of each received block is not known a priori, the probability of receiving a block at a given speed can be determined. As mentioned above, a variable speed vocoder, encodes each voice block and one of a set of predetermined speeds based on the vocal activity during the time interval. Since the characteristics of vocal activity can be modeled, > probabilistic functions can be derived from the model of data rates that depend on vocal activity. Hypothesis tests based on the probabilistic functions of the data rates can then be designed to determine the most probable data rate for each block of data received. The use of hypothesis testing to determine the speed in a variable speed receiver system can be best determined by referring to FIGURE 2. In a CDMA environment, for example, the receiver system 50 of FIGURE 2 can be implemented in a mobile unit or in a cell-site to determine the data rate of the received signals. The present invention offers particular advantages, because it avoids exhaustive decoding at all speeds. By choosing a hypothesis and verifying the hypothesis for corrections, the average amount of processing of each block received is reduced. This is especially important in the mobile unit, because the reduced processing, and therefore, the power consumption, in the decoding process can extend the life of the battery in the receiver. The variable speed receiver system 50 illustrated in FIGURE 2 includes the receiver 30 for collecting the transmitted signals, including the data signal of interest. The receiver 30 amplifies and converts in a downward manner by frequency, the signals received from the RF frequency band to the intermediate frequency (IF) band. The IF signals are presented to the demodulator 32. The design and implementation of the demodulator 32 are described in detail in U.S. Patent No. 5,490,165, entitled "ALLOCATION OF DEMODULATION ELEMENT IN A SYSTEM CAPABLE OF RECEIVING MULTIPLE SIGNALS", issued on February 6, 1996, and granted to the beneficiary of the present invention, the description of which is incorporated herein by reference. The demodulator 32 demodulates the IF signal to produce a data signal consisting of the symbols of a data block. The demodulator 32 generates the data signal by compressing and correlating the IF signal directed to the receiver. The demodulated data signal is then fed to a buffer 33. The buffer 33 stores the demodulated data signal, or received symbols, until appropriately decoded. The buffer 33 can also be the deinterleaver if the data block has been interleaved for transmission. The buffer 33 provides the demodulated symbol data to the decoder 34. The hypothesis test module 36 implements the hypothesis test to determine the data rate of a received data block. The hypothesis testing module 36 comprises the processor 40, which includes the memory 38. The information necessary in the hypothesis test, such as the decoded speeds of the previous blocks and the probabilities, are stored in the memory 38. For each received data block, the processor 40 determines the most probable speed based on the information stored in the memory 38. The processor 40 then presents the most probable data rate to the decoder 34, which decodes the data signal at its fastest speed. likely to produce decoded bits. In the exemplary embodiment, the decoder 34 is a trellis decoder, capable of decoding variable rate data, such as a Viterbi decoder. The design and implementation of a multi-speed Viterbi decoder, which comprehensively decodes a received signal at all speeds of a set of speeds, is described in the aforementioned US Patent Applications 08 / 233,570 and 08 / 126,477. It should be understood by one skilled in the art that the multi-speed Viterbi decoder can be modified to decode at a selected speed. This can be achieved by having the Viterbi decoder receive a speed indicator input, in response to which the decoder decodes the data signal according to the speed indicator. In this way, the modified Viterbi decoder can decode a received data block based on a speed indicator supplied by the processor 40 of the hypothesis testing module 36. The decoder 34 generates bits of information data and error metrics that characterize the information bits. The error metrics include the CRC bits described above, which were added to the data blocks as supplementary bits. The decoder 34 can also generate other error metrics, such as Yamamoto Quality Metric and Symbol Error Percentage (SER). The Yamamoto metric is determined by comparing the differences in the metrics or the intercalation paths in each step of the Viterbi decoding with a threshold, and marking a path or path as unreliable, if the difference of the metric is less than a quality threshold. If the final path selected by the Viterbi decoder has been marked as not reliable at any step, the encoder output is marked as not reliable. Otherwise, it is marked as reliable. The Symbols Error Percentage > it is determined by taking the decoded bits, recoding those bits to provide recoded symbols and comparing those recoded symbols with the received symbols that are stored in the buffer 33. The BE is a measure of the similarity between the recoded symbols and the received symbols. The recoded information bits and error metrics are provided to the data checking element 42, which determines whether the information bits have been decoded correctly. In a preferred embodiment, the data checking element 42, first checks the CRC bits. If the CRC check fails, then the data verifying element 42 provides a signal indicative of the failure to the processor 40. ' If the CRC check passes, then the data checking element 42 determines whether the recoded BE is below a certain threshold. If the SER is above the threshold, then a signal indicative of the failure to the processor 40 is provided. Otherwise, it is determined that the data rate provided by the hypothesis test module 36 is correct, and a successful signal to the processor 40, after which no further decoding is performed on the data blocks. The decoded data signal is appropriately presented to the variable speed vocoder 44. When the processor 40 receives a fault signal indicating that the data symbols have not been properly decoded in the information bits, the processor 40 will determine at least another speed data set of data rates, to which to decode the data symbols. The processor 40 provides the speed information to the decoder 34, which decodes the data symbols at the provided rate. For each data rate at which the data signal is decoded, the data verifying element 42 will determine the quality of the decoded information bits. After the determination made by the data verifying element 42, that the correct data rate has been found, a signal of the decoded information bits is provided to the variable speed vocoder 4. The vocoder 44 will then process the information bits to interconnect them with the user. The hypothesis test module 36 can implement any of a number of hypothesis tests to determine the data rate of a received data block. For example, hypothesis testing can be based on known statistics of vocal activity. It is known that for a four speed set that uses blocks of 20 ms, a full speed block will usually be followed by another full speed block, while a block of an eighth speed will usually be followed by another block one eighth of a second. speed. In addition, it is also known that most blocks will be either full speed or one eighth speed, instead of half or quarter speed, because there are no periods of voice and silence in bursts of 20 ms. Based on these characteristics, the hypothesis test can designate the speed of the previous data blocks as the most probable speed for the currently received data block. In an exemplary implementation, the speed of the previous data block is stored in the memory 38 of the hypothesis test module 36. When a data block is received, the processor 40 of the hypothesis test module 36 obtains the block rate of the memory 38 and presents it to the decoder 34. The decoder 34 decodes the data block received at the speed of the previous block to produce information bits. The decoder 34 also generates error metrics, which are then presented to the data checking element 42 together with the information bits. If the data verifying element 42 determines from the error metrics that the decoded bits are of good quality, then the information bits are presented to the vocoder 44. Otherwise, a failure indication of the data verifying element 42 is sent to the processor 40. The processor 40 can then cause the decoder 34 to exhaustively decode the data block a all other speeds, before determining the data rate. A flow chart illustrating some of the steps involved in determining the speed, as described in the previous embodiment, is shown in FIGURE 3. Alternatively, the processor 40 may cause the decoder 34 to decode the block sequentially. of data, according to statistics of the next most likely speed at the least probable speed. Statistics can be determined in numerous ways, such as, according to the probability distributions described below. For each coding, error metrics are generated by the decoder 34 and verified by the data checking element 42 for correction. When decoded correctly, the decoded block is passed to the vocoder 44. A flow chart illustrating some of the processing steps of this mode is shown in FIGURE 4. Another implementation of the hypothesis test module 36 is based on the a priori probability distribution of data rates. For a set of four speeds, the a priori probability distribution (P) of the data rates can be defined as: P = Prob { Rt.}. , (3) where Rt refers to the full speed, average, a quarter, or an eighth of speed at time t. The probability of receiving a block at each of the different data rates of a set of speeds is conserved in the memory 38 of the processor 40. In general, the probability distribution of the data rates is determined based on statistics Theoretical or empirical statistics of vocal activity. The probability of receiving a block at the different speeds is then stored permanently in the memory 38, to determine the speed of each received data block. In a more sophisticated mode, the probability of the speeds stored in the memory 38 can be updated based on the actual statistics of the received data blocks. For each new received data block, the processor 40 obtains the most probable rate of the memory 38 and presents the most probable rate to the decoder 34. The decoder 34 decodes the data signal at its most probable data rate and presents the decoded data. to the data checking element 42. The error metrics, including the CRC, are also generated by the decoder 34 and presented to the data checking element 42. Other error metrics can also be generated to be verified by the data checking element 42 If the error metrics indicate that the decoded bits are of good quality, then the information bits are presented to the vocoder 44. Otherwise, a failure indication of the data checking element 42 is sent to the processor 40. Next, processor 40 obtains the second most probable data rate from memory 38 and presents this to decoder 34, and the dec process Write and check errors continues until the correct data rate is found. A flowchart of the processing steps of this embodiment is illustrated in FIGURE 5. Alternatively, after receipt of a trouble signal by the processor 40, the processor 40 can cause the decoder 34 to exhaustively decode the data block at each of the other data speeds of the speed set, and the error metrics are verified for each decoding, to determine the actual transmission speed. A flow chart of the processing steps of this mode is illustrated in FIGURE 6. Instead of designating the hypothesis test based on a simple probability distribution of the data rates, conditional probabilities can be used to improve the accuracy of speed determination. For example, the probability of receiving a block of data at a given speed can be defined, so that it is conditioned on the actual speeds of the previous data block. Conditional probabilities based on previous speeds work well, because the transition characteristics of the data signals are well known. For example, if the speed of two blocks back was an eighth of speed and the speed for the previous block was half speed, then the most probable speed for the current block is full speed, because the transition to half speed indicates the presence of active voice. On the contrary, if the speed of two blocks back was the full speed and the speed for the previous block was a quarter of speed, then the most probable speed for the present block can be an eighth of speed, because the transition of Speed indicates the presence of silence. The probability distribution of the conditioned data rates over the speeds of n previous data blocks can be defined as: P = Prob { Rt I Rt-i, Rt_2, ..., Rt-n} (4) where Rt again refers to the velocity at time t, and Rt ~? -2 / • • • / • Rt-n refers to the speeds of n previous data blocks for n >; 1. The probability of receiving a block at each of the different data rates of a set of conditional speeds, over the n previous actual speeds, is stored in the memory 38 of the processor 40. In addition, the actual data rates of the Prior data blocks are kept by the processor 40, and can be stored in the memory 38 when the speeds have been determined. For each received data block, the processor 40 will determine the most probable data rate conditioned on the n previous actual data rates and present it to the decoder 34. The decoder 34 will decode the block at its most probable data rate and present the bits decoded to the data checking element 42. In addition, error metrics are generated by the decoder 34 and presented to the data checking element 42. If the error metrics indicate, that the decoded bits are of good quality, then the information bits are presented to the vocoder 44. Also, the processor 40 is informed of the speed decision, so that it can maintain the history of chosen speeds. That is, the processor 40 is fed with Rt, so that it can be used to determine Prob { Rt I Rt-i * Rt-2 * • - • r Rt-n} for the next block. If the error metrics indicate an unsuccessful decoding, then a failure indication signal of the data verifying element 42 is sent to the processor 40, and the processor 40 determines the second most likely data rate conditional on the n previous data rates , to decode the data block. As in the case of simple probabilities, the process of decoding and verifying errors continues until the correct data rate is found. Some of the processing data of this embodiment are illustrated in a flowchart in FIGURE 7. Also, as in the case of simple probabilities, after a failed decoding at the most probable rate, the decoder 34 can decode exhaustively block the data to all other data rates and have the error metrics checked for all decoding to determine the data rate. Some of the processing steps for this modality are illustrated in a flow chart in FIGURE 8. It should be understood that the conditional probability distribution of the data rates may depend on other statistics than the actual velocities of the data blocks. previous data. For example, the probability distribution can be conditioned on one or more of the quality measurements of the block. The probability distribution is then defined as: P = Prob { Rt | X ?, X2, ..., Xk} (5) where Rt is the velocity at time t, and Xi, X2, ..., Xk are one or more measurements of block quality. The quality measurements of the block k may be measurements made on the current data block, or measurements made on previous data blocks, or a combination of both. An example of a block quality measurement is the SER error metric referred to above. In this way, the probability of receiving a block at a given speed is conditioned on the SER obtained from the previous decoding, if a previous decoding has been carried out. The conditional probability distribution can also depend on the combination of the actual speeds of the previous data blocks and the measurements of block quality. In this case, the probability distribution of the data rates is defined as: Pt = Prob { Rt I Rt- ?, Rt-2, ..., Rt-n, Xi, X2 r. . . , Xk} (6) where Rt is the velocity at time t, Rt- ?, Rt-2, ..., Rt-n are the velocities of the previous blocks of data and Xi, X2, ..., Xk are the measurements of block quality. In cases where the probability distribution was based on the block quality measurements, the block quality measurements should be maintained in the processor 40 of the hypothesis testing module 36, as can be seen from the previous description , the hypothetical speed of the block can be conditioned on a number of different statistics, and the speeds of the previous blocks and the block quality measurements are examples of those statistics. For each received data block, the processor 40 uses the statistics to determine the rate at which to decode the block. An additional refinement in the determination of the speed at which a block of received data is decoded, considers the costs of processing the decoding of the block at various speeds, in conjunction with the hypothesis test. In this modality, an optimal test sequence of the velocities was established, based on both the probability distribution of. data rates as the cost of decoding each of the data rates. The optimal test sequence is maintained by the processor 40, which causes the decoder 34 to sequentially decode a received data block, according to the optimal sequence until the correct speed is found. The optimal test sequence is set to minimize the expected total cost of the speed search. Denoting P as the probability that the speed search will stop at the Ti test, and d is the cost to conduct the test i, the total expected cost of the speed search, using the test sequence Tl r T2, ... , TM, where M is the number of possible speeds in the system and 1 < i < M, can be modeled as: + C2) * P2 + (Ci + C2 + • •. + CM) * PM [7) The optimal test sequence is found by minimizing the expected total Ctotai cost. In Equation (7), the cost Ci to drive the T¿ test will generally be the processing power required to decode a block at the speed specified by the Ti test. The cost can be allocated to be proportional to the speed of the block specified by the Tír test because the computational complexity of the decoder 34 is in general approximately proportional to the number of bits per block. The probabilities Pi can be assigned with an unconstrained a priori probability distribution of the data rates, as defined by the Equation (3), or any of the conditional probability distributions defined by the equations (4), (5), or (6) above. In a variable speed communication system, where data blocks are transmitted at 9,600 bps, 4,800 bps, 2,400 bps, and 1,200 bps, the following examples illustrate the formulation of the optimal test sequence for the determination of the velocity of a block received. It is assumed that the costs of decoding blocks of 9,600 bps, 4,800 bps, 2,400 bps, and 1,200 bps are 9.6, 4.8, 2.4, and 1.2, respectively. In addition, it is assumed that the probability of receiving a block at each of the four speeds is the a priori probability not conditioned of having the following values: Prob (9,600 bps) = 0.291, (8) Prob (4,800 bps) = 0.039, (9) Prob (2,400 bps) = 0.072, and (10) Prob (l, 200 bps) = 0.598, (11) The probabilities given in Equations (8) - (11) were derived from empirical steady-state data. A list of all possible test sequences for speed determination in the system transmitting blocks at 9,600, 4,800, 2,400 and 1,200 bps is shown in Table I below. In table I, column 1 lists all the possible test sequences Ti, T2, T3, T4, where T ± = l refers to the decoding test at 9, 600 bps, Ti = l / 2 refers to the decoding test at 4,800 bps, T? = l / 4 refers to the decode test at 2,400 bps, and Ti = l / 8 refers to the decode test at 1,200 bps. Columns 2 and 3 list the probability Pi and the cost Cx to perform the Tx test, columns 4 and 5 list the probability P2 and the cost C2 to perform the test T2, columns 6 and 7 list the probability P3 and the cost C3 to perform the test T3, and columns 8 and 9 list the probability P and the cost C4 to perform the test T4. The total cost Ctotai to carry out the test sequence TX / T2, T3, T4 is listed in column 10. / 2, 1, 1/4, 0.039 0.291 0.072 0.598 16.3 / 8 4 .8 9 .6 2 .4 1 .2 5 / 2, 1, 1/8, 0 .039 0 .291 0 .598 0 .072 15.0 / 4 4 .8 9 .6 1 .2 2 .4 0 / 2, 1/4, 1, 0 .039 0 .072 0 .291 0 .598 16.3 / 8 4 .8 2 .4 9 .6 1 .2 6 / 2, 1/4, 1/8, 0 .039 0 .072 0 .598 0 .291 10.9 4 .8 2 .4 1 .2 9 .6 7 / 2, 1/8, 1, 0 .039 0 .598 0 .291 0 .072 9.61 / 4 4 .8 1 .2 9 .6 2 .4 / 2, 1/8, 1/4, 0 039 0 .598 0 072 0 .291 9.62 4 .8 1 2 2 4 9 .6 / 4, 1, 1/2, 0. 072 0 291 0. 039 0 598 15.0 / 8 2. 4 9. 6 4. 8 1. 2 8 / 4, 1, 1/8, 0. 072 0. 291 0. 598 0. 039 12.2 / 2 2. 4 9. 6 1. 2 4. 8 6 / 4, 1/2, 1, 0. 072 0. 039 0. 291 0. 598 16.1 / 8 2. 4 4. 8 9. 6 1. 2 1 / 4, 1/2, 1/8, 0. 072 0. 039 0. 598 0. 291 10.7 2. 4 4. 8 1. 2 9. 6 1 / 4, 1/8, 1/2, 0. 072 0. 598 0. 039 0. 291 7.89 2. 4 1. 2 4. 8 9. 6 Table I As shown in Table I, the test sequence optimal is the sequence 1/8, 1, 1/4, 1/2 shown in the 19th row. This test sequence offers the lowest expected total cost of processing. Therefore, the speed determination system would decode a received data block at 1,200 bps first. If decoding at 1,200 bps is not successful, then the block would be decoded sequentially at 9,600 bps, 2,400 bps, and 4,800 bps, until the correct speed is found. In a preferred embodiment, the optimal test sequence is preserved by the processor 40 of the hypothesis testing module 36. For each received data block, the processor 40 causes the decoder 34 to decode the block sequentially, according to the sequence of optimal test, with each decoding verified by the data checking element 42, until the correct data rate is found. The processing resources are used efficiently in this speed determination system, because the decoding is carried out sequentially according to an optimal search sequence. Based on the modalities described above, it should be understood by those skilled in the art, that the present invention is applicable to all systems, in which data has been decoded according to a variable speed scheme and the data must be decoded to determine the speed. Even more generally, the invention is applicable to all systems in which the coded data E is a function of the data D and some key k, and there is still information in D or E that allows the verification of the correct D by the receiver. The sequence k may vary over time. The encoded data are represented as: E = f (D, k) (1) where k is from a small K set of keys and where there is some probability function on the set of keys. The reverse of coding, or decoding, can be represented as: E = f1 (E, k) (2) where k was chosen so that D is correct. As an example, assume that D are the composite data of the fixed-length DI sequence and the fixed-length sequence D2, so that D = DI, D2. The sequence D2 is the Code of Cyclic Redundancy (CRC) of DI, so that D2 = fcrc (di). Assume also that the coding function, f (D,), is an exclusive O of a fixed length D with the fixed length sequence k. Then, the decoding, f1 (E k), would be the exclusive 0 of E with the correct k. The correct k is verified by checking if D2 = fcrc (DI). The correct k can be found by decoding all possible k in K and then determining if the CRC check passes. Alternatively, this can be done by decoding sequentially using a k at a time, without further decoding once the "correct" k is found. According to the present invention, the order of the sequential decoding must be determined by the hypothesis test. Numerous hypothesis tests can be used, including the tests described above. The order of sequential decoding may depend, in addition, the cost of processing, as described above. The use of hypothesis testing and / or cost functions in the formulation of a test sequence for determining the speed reduces the average amount of processing, since fewer k will be attempted. The above description of the preferred embodiments is provided to enable any person skilled in the art to make use of the present invention. The different modifications of those modalities will be readily apparent to those skilled in the art, and the generic principles defined herein, may be applied to other modalities without the use of an inventive faculty. Thus, it is intended that the present invention not be limited to the modalities shown herein, but according to the broadest scope consistent with the principles and novel features described herein. It is noted that in relation to this date, the best method known to the applicant to carry out the aforementioned invention, is that which is clear from the present description of the invention.

Claims (34)

CLAIMS Having described the invention as above, the content of the following claims is claimed as property.

1. In a variable speed communication system, a subsystem for determining, in a receiver, the data rate of a received data block, characterized in that it comprises: a processor for generating a signal indicating the most probable speed of the received data block , according to a predetermined hypothesis test; and a decoder for receiving the signal of the most probable rate and for decoding the received data block in a decoded block of bits at the most probable rate.

2. The speed determination subsystem according to claim 1, characterized in that the most probable speed is the speed of the previous data block.

3. The speed determination subsystem according to claim 1, characterized in that the hypothesis test is based on an a priori probability distribution of the data rates.

4. The speed determination subsystem according to claim 1, characterized in that the hypothesis test is based on a conditional probability distribution of the conditioned data rates on the speeds of at least one previous data block. 5. .

The speed determination subsystem according to claim 1, characterized in that the hypothesis test is based on a conditional probability distribution of conditioned data rates on at least one quality measurement of the block.

The speed determination subsystem according to claim 1, characterized in that it further comprises a data verifier element for receiving the decoded bits, generating error metrics characterizing the decoded bits, and generating a quality indication, based on the error metrics for the decoded bits.

The speed determination subsystem according to claim 6, characterized in that it further comprises a vocoder for receiving the decoded bits and processing the decoded bits to provide voice to a user, after generating a positive indication of the quality; and wherein after the generation of a negative indication of quality, the processor further makes the decoder perform the additional decoding of the received data block according to at least one speed different from the most probable speed.

The speed determination subsystem according to claim 7, characterized in that the additional decoding is performed sequentially according to a predetermined test sequence of the data rates; wherein the data verifying element generates error metrics for each additional decoding and generates a quality indication based on the error metrics for each additional decoding; and where the additional decoding ends after the generation of a positive indication of quality.

The speed determination subsystem according to claim 7, characterized in that the additional decoding comprises the exhaustive decoding of the received data block at all speeds of a set of speeds, except the most probable speed; and wherein the data checking element generates error metrics for each additional decoding and determines the speed of the data block received in accordance with the error metrics.

The speed determination subsystem according to claim 6, characterized in that the error metrics include a result of Cyclic Redundancy Verification.

The speed determination subsystem according to claim 6, characterized in that the error metrics include a metric of the Symbol Error Percentage.

12. The speed determination subsystem according to claim 6, characterized in that the error metrics include a Yamamoto quality metric.

The speed determination subsystem according to claim 1, characterized in that the processor comprises a memory for storing the most probable speed.

The speed determination subsystem according to claim 1, characterized in that the decoder is a Viterbi decoder.

15. In a variable speed communication system, a subsystem for determining, in a receiver, the data rate of a received data block, characterized in that it comprises: a processor for generating a data rate test sequence, to determine the speed of a received data block, the test sequence is generated according to a predetermined hypothesis test; a decoder for decoding the data block received sequentially, according to the test sequence and generating a decoded block of bits for each speed at which the received data block is decoded; a data verifying element for generating error metrics characterizing the decoded bits and for generating a quality indication, based on the error metrics for each speed at which the received data block is decoded; and where no additional decoding is performed after the generation of a positive indication of quality.

16. The speed determination subsystem according to claim 15, characterized in that the hypothesis test is based on an a priori probability distribution of the data rates.

17. The speed determination subsystem according to claim 15, characterized in that the hypothesis test is based on a conditional probability distribution of the data rates conditioned on the speed of at least one previous data block.

18. The speed determination subsystem according to claim 15, characterized in that the hypothesis test is based on a conditional probability distribution of the conditioned data rates on at least one measurement of the quality of the block.

19. The speed determination subsystem according to claim 16, characterized > in addition, the test sequence is generated according to the cost of decoding the data block received at each of the data rates.

20. The speed determination subsystem according to claim 17, characterized in that the test sequence is further generated in accordance with the cost of decoding the data block received at each of the data rates.

21. The speed determination subsystem according to claim 18, characterized in that the test sequence is further generated in accordance with the cost of decoding the data block received at each of the data rates.

22. The speed determination subsystem according to claim 15, characterized in that it further comprises a vocoder for receiving the decoded bits and processing the decoded bits to provide voice to a user, after generating a positive indication of the quality.

23. The speed determination subsystem according to claim 15, characterized in that the error metrics include a Cyclic Redundancy Verification result.

24. The speed determination subsystem according to claim 15, characterized > because the error metrics include a metric of the Symbol Error Percentage.

25. The speed determination subsystem according to claim 15, characterized in that the error metrics include a Yamamoto quality metric.

26. The speed determination subsystem according to claim 15, characterized in that the processor comprises a memory for storing the test sequence of the data rates.

27. The speed determination subsystem according to claim 15, characterized in that the decoder is a Viterbi decoder.

28. A method for determining the speed of a data block received in a variable speed communication system, characterized in that it comprises the steps of: receiving a broadband signal; demodulating the broadband signal to produce a data signal, wherein the data signal has been transmitted to one of a set of possible transmission rates; generate a test sequence of the data rates, to determine the speed of the data signal, the test sequence is generated according to a predetermined hypothesis test; decoding the data signal sequentially, according to the test sequence to generate a decoded block of bits for each speed at which the data signal has been decoded; generate error metrics that characterize the decoded block of bits for each speed at which the data signal is decoded; generate a quality indicator based on the error metrics of each speed at which the data signal is decoded; and after generating a positive quality indication, provide the decoded block of bits to a vocoder, which processes the decoded bits to provide voice to a user.

29. The method according to claim 28, characterized in that the hypothesis test is based on an a priori probability distribution of the data rates.

30. The method according to claim 28, characterized in that the hypothesis test is based on a conditional probability distribution of the data rates conditioned on the speed of at least one previous data block.

31. The method according to claim 28, characterized in that the hypothesis test is based on a conditional probability distribution of the conditioned data rates on at least one quality measurement of the block.

32. The method according to claim 29, characterized in that the test sequence is also generated in accordance with the cost of decoding the data block received at each of the data rates.

33. The method according to claim 30, characterized in that the test sequence is also generated in accordance with the cost of decoding the data block received at each of the data rates.

34. The method according to claim 31, characterized in that the test sequence is also generated in accordance with the cost of decoding the data block received at each of the data rates. SUMMARY OF THE INVENTION A system and method for determining the data rate of a data block in a receiver (50) of a variable speed communication system. A vocoder in a transmitter encodes a block of data at one of the speeds of a predetermined set of speeds. The data rate depends on the vocal activity during the time interval of the data. Data blocks are also formatted with supplementary bits, including bits for error detection and correction. In the receiver (50), the data rate for the block is determined based on hypothesis tests. Because the data rate is based on vocal activity, a hypothesis test can be designed based on the vocal activity statistics. The received data block is first decoded by a decoder (34) in information bits at the most probable speed, according to the information provided by the hypothesis test module (36). The data checking element (42) generates error metrics for the decoded information bits. If the error metrics indicate that the information bits are of good quality, then the information bits are presented to a vocoder (44) in the receiver, to be processed to interconnect them with the user. If the error metrics indicate that the information bits have not been appropriately coded, then the decoder (34) decodes the received data block at the other speeds of the speed set, until the actual data rate is determined.