MXPA96002939A - Apparatus and method to create a similar video auna pelic - Google Patents

Abstract

The present invention relates to a video camera comprising: (a) a non-interlaced video signal image forming element, (b) an analog conditioning circuit for amplifying and band-limiting a non-interlaced video signal generated by the image forming element of the non-interlaced video signal; (c) an analog-to-digital converter for converting the non-interlaced video signal to a digitally represented signal; (d) a memory circuit comprising a plurality of groups of memory for storing the digitally represented signal; (e) a post-conditioning circuit for introducing the grain to the digitally represented signal; (f) a digital-to-analog converter for converting the digitally represented signal into an interlaced signal; ) a synchronization and control circuit to synchronize the conversion of the non-interlaced video signal into the digitally represented signal and the conversion of the signal represented digitally in an interlaced signal to store and remove the digitally represented signal to and from the memory circuit, and to synchronize the addition of the

Description

"APPARATUS AND METHOD TO CREATE A VIDEO LIKE A MOVIE" TECHNICAL FIELD The present invention is directed to a video camera and a method for simulating the broadcast aspect of a motion picture film. More specifically, the invention provides a design and method of video camera for simulation of real-time digital video of the cinematographic film.

ANTECEDENTS OF THE TECHNIQUE It can be generally believed that television broadcasts provide two different "aspects". Viewers of broadcasts can commonly tell the difference between the appearance of a video camera broadcast and the aspect of broadcasting a motion picture. For example, news, game shows and evening soap operas are typically filmed on video cameras whose signals are recorded on a videotape. In contrast, programming broadcasts that originated in a motion picture are often thought to present a different and richer "look" than that of a video camera broadcast. The motion picture is commonly transferred to a video tape for editing and broadcast purposes. However, even under these circumstances, the motion picture retains the unique "look" of the movie. This richer aspect is associated with a more expensive higher quality production process of a motion picture compared to the appearance of a recorded broadcast of a video camera. The production of works that originate in a film usually costs three to five times more than the production of a work originated from video. In addition, the production of a motion picture frequently requires gang positions and film equipment that is much more expensive than videodifusion equipment. The visually perceptible difference between the appearance of a broadcast made on a conventional video camera and the appearance of a broadcast made from a film that has been transferred or converted into a video signal, may be important for the nature of the work that is being done. is creating and the medium where it is destined to spread, as well as the market, which is trying to reach. This difference in appearance between these two methodologies is attributable in part to the differences between the way in which the conventional video camera captures and displays images compared to the way in which the motion picture camera does. A first difference between a video camera broadcast and a film film broadcast transferred or converted to a video signal is related to the way in which the video camera captures or freezes time compared to the way the camera of the motion picture captures or freezes time. A second difference in diffusion performance between these two methodologies is related to the contribution of the film emulsion gain with respect to the visual appearance of a film. A conventional video camera captures the action as a series of horizontal electronic scans of a photosensitive pickup tube or a solid state-loaded (CCD) coupled device type image sensor. The action in front of the lens of the video camera is sent as a series of interlaced fields or half frames. Two video fields are required to constitute a complete video frame. The first video field consists of the odd number scan lines, while the second video field consists of even number scan lines. In the United States and other countries, the use of 60 Hz energy, a diffusion field regime is about 60 fields per second, which yields a frame rate of approximately 30 frames per second. A motion picture camera captures the action as a series of still photographs by opening and closing the camera shutter at a predetermined rate. When seen in rapid succession, these fixed images create the illusion of movement. In the United States and in most other countries that have an energy of 60 Hz, the normal camera and the speed of projection of the film is 24 frames per second. Those countries that have an energy of 50 Hz, use 25 frames per second as their normal film projection speed. In order to watch the motion picture on a conventional video system of the National Television Standards Committee (NTSC), the 24 film images per second must be converted into 60 video fields (or 30 video frames) per second. This video film conversion process requires that 6 additional video frames be created every second of the motion picture of 24 frames per second, conventionally, these 6 frames of extra video per second are created by scanning each other movie image for 3 fields instead of two fields. This process of converting 24 second images to 30 frames of video per second is called the "3-2 conversion". This process is well known in the broadcast industry as the methodology to convert film into video for broadcast. With a conventional video camera, a second of time produces 60 independent video fields. By dividing each second in 60 separate video fields, the conventional video camera yields a uniform continuity of movement when it diffuses. For those countries and locations that do not use NTSC television systems, such as the United Kingdom and most of Europe, the 3-2 conversion process is not used. This is so because the cinematographic film in these countries is photographed and projected at 25 frames per second, where each frame of the film yields two video fields, or a complete video frame. Occasionally, the film so that the broadcast is photographed at an increased image capture rate of 30 frames per second. When this is done, the need for 3-2 conversion to transfer the movie to video is eliminated. The video film 3-2 conversion process creates a video sequence through which the movement within the scenes of the original film is displayed discontinuously. The viewer of this broadcast can observe a "step" or "jump" action for the fast movement within the scenes of the original movie. In contrast, due to the way in which video cameras capture images, this step or jump action is not detected in its majority. As mentioned above, the second predominant factor that contributes to the appearance of the motion picture is the medium of film itself. The photochemistry of the emulsion of the light-sensitive film coating the film results in a grainy image. The grain of the film medium appears as random patterns particles of similar size, located in areas of similar exposure and density. The localized random patterns of particles create a microscopic mosaic that produces a visual "texture" that is associated with the appearance of the motion picture. Since each film image is photographed and revealed from a different piece of film material, the precise placement of the grain particle is singularly different from frame to frame even when grain intensity tends to be similar. As a result, even the shooting of a static scene will yield a granularity that constantly changes in the middle of the film. The intensity of the grain effect may vary depending on the material of the film. The material of the film with a higher sensitivity to light, in general, exhibits more visible grains than the film that is less sensitive to light. Electronic noise of a certain level is usually produced by all video cameras. Some forms of high frequency random noise may appear as a kind of granularity in video systems. Nevertheless, this type of granularity is not of the same degree and nature, visually, as is the granularity created by the photochemistry of a cinematographic film. Random electronic noise has no spatial dependence and, in general, it is only one height of a scan line. The visual differences between the diffusions of works originally created in video cameras compared to those created using a motion picture film or movie film cameras are well known to those skilled in the art. The main causes of these differences, as described above, are used in connection with the present invention to provide a video camera for real-time simulation of the visual appearance of the motion picture that has been transferred or converted. in a video signal, as well as a method to perform this simulation. The desirability of producing film quality broadcasts through a video medium has long existed and several attempts have been made to achieve these and other related objects, none of which employ the elements and singular steps of the present invention. A method and apparatus for simulating video image film is described in U.S. Patent No. 4,935,816, issued to Faber, the disclosure of which is incorporated herein by reference. Faber discloses a method and apparatus for receiving a conventional video signal from a pre-recorded videotape or a conventional video camera and processing the signal to provide the appearance of an image recorded in a motion picture to be sent directly for broadcast or record in a videotape. Faber reveals that the video of the recorded images contains no grain and that the noise or "snow" in the video system is typically undesirable. Faber says that extensive electronic filtering is used to eliminate noise from electronic circuits and cameras, recording devices and television sets for a clear image. Faber identifies three basic approaches to recording motion pictures; (1) photographic film exposed using a camera for cinematographic films that is revealed and printed towards the projection film, which can then be shown using a projector and screen; (2) recording on magnetic video tape where images have been recorded directly on the magnetic tape from a television or video camera; and (3) video and videotape cameras used for the initial registration of the images of the cinematographic film followed by the disintegration of the video recorded in the red, green and blue components that are then scanned into the photographic film that is then processed and it is returned to the videotape using the "telecine" process. Faber indicates that each of these approaches has certain technical limitations and undesirable costs associated with them. Faber's solution to these inconveniences is to admit a video signal from a prerecorded video camera or video tape and divide it to provide a first real-time signal for image information and a second real-time signal for synchronization. and color burst information and a first delayed signal and a second delayed signal. Faber provides white filter noise limited in amplitude with the portion of the image of the first real-time signal to simulate the "grain" of the film and then forms two interrelated fields that are sent through a third delay equal in length to the first delay. By repeating in sequence the interpolation of fields to be synchronized with predetermined delays, when processed, the resulting video output comprises five field sets wherein each of the first four fields is an interpolation of a pair of successive previous frames, while that the fifth field is a repetition of the third interpolated field. Commercial efforts to create film-like video cameras include a product known as I egami EC 35 and a CEI / Panavision video camera. These two commercial products were introduced in the early 1980s and both used a similar concept to try to adapt a film lens to a modified hand tube type color camera. The external appearance of these two commercial products was similar to a film camera, but the output images were generally on par with a higher quality video camera and were not effective in simulating the appearance of a motion picture camera. None of the above-described attempts to create a video signal that can emulate the appearance of the motion picture has been successful in creating a commercial and effective product having attributes of the present invention, which will be described below.

EXHIBITION OF THE INVENTION The inconveniences of the prior art can be considerably reduced or eliminated using the present invention. In accordance with the present invention, a video camera is provided for real-time simulation of the visual appearance of the motion picture that has been transferred or converted into a video signal. The video camera simulates the effect of a shutter of the motion picture camera using non-interlaced scanning of the solid state image sensors. The data of each complete image scan is stored digitally in the memory of the local camera, and then read from the local memory at the desired speed. The camera and method of the present invention then combine the stored video signal with a two-dimensional digital grain effect generator before being sent to a conventional interlaced video signal. A method for creating the broadcast aspect of the motion picture is provided wherein the method comprises the steps of increasing the scan rate of the CCD image sensors and sending non-interlaced video images, converting the video images from the analog form To digitalize, write video images in memory, read video images from memory to a video output data bus at pre-set regimes, add a selectively adjustable amount of two-dimensional electronic artifacts to simulate the grain of the film, and convert video images from digital to analog form for broadcast or videotape recording. The local memory and the associated control circuit of the present invention provides a 3-2 simulation of a film transfer of 24 frames per second as well as a 1 to 1 simulation of a motion picture film that was shot and transferred to the videotape at a rate of 30 frames per second. The present invention also provides a video memory that has the ability to freeze a full resolution video frame. In the present invention, since the image is stored digitally, a simulation of the grain of the film can be added as a two-dimensional random mosaic structure before the digital video becomes a conventional interlaced output signal. A grain effect circuit is provided that allows adjustment of grain size and quantity in order to simulate various emulsions and film effects. An object of the invention is to provide a video camera that can be used to create video outputs that emit the appearance of the motion picture, whether in black and white or in colors. A further object of the present invention is to provide a method for creating the appearance of a motion picture that has been transferred to video. Yet another aspect of the present invention is to provide a method that operates in a non-interleaved sequence mode at increased scan rates to provide an electronically adjustable bead generator to the video signal, which has a capability to write to memory in a mode increased non-interlaced speed and at the same time read from memory in a conventional NTSC interlaced television mode, to provide a selectable switch method in order to create the simulated appearance of the motion picture and provide capable video memory circuits to freeze a full resolution video image. Still another object of the present invention is to produce a camera and method that operate within the PAL and SECAM standards of the United Kingdom and France, respectively, as well as to produce the camera and method claimed herein that functions in conjunction with a television. High definition (HDTV). A still further object of the present invention is to reduce production costs to generate video output signals that provide quality aspects of a motion picture film and to reduce the amount of time needed between shooting a scene and creating an output. of quality video of cinematographic films for edition and diffusion purposes. These and other objects of the present invention will be more fully understood by reference to the drawings and the detailed description of the invention which is pointed out herein.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 illustrates a comparison of how time is captured at two different speeds in the motion picture and in a prior art video camera. Figure 2 illustrates how the motion picture film shot at 24 frames per second is transferred to a 30 frame per second video tape that is also known as the 3-2 transfer. Figure 3 illustrates the way in which the film shot at 30 frames per second transfers the 30 frames per second video tape also known as a 1 to 1 transfer. Figure 4 illustrates a functional flow diagram showing the elements and total steps of the present invention, including their interrelation. Figure 5 illustrates a functional flow diagram of an analog signal input conditioning circuit. Figure 6 illustrates a functional flow diagram of an analog-to-digital converter circuit. Figure 7 illustrates a functional flow diagram of a synchronization and control circuit. Figure 8 illustrates a functional flow diagram of a multiplexer address and memory control circuit that includes three high-speed field memory blanks.

Figure 9 illustrates a functional flow diagram of a digital post-conditioning processing circuit. Figure 10 illustrates a flow chart of a digital-to-analog converter circuit. Figure 11 is made up of tables describing the memory read and write cycles of the devices present when simulating a film that was shot at 30 frames per second and at 24 frames per second.

BEST WAY TO CARRY OUT THE INVENTION The camera and method of the present invention use a non-interlaced image sensor to capture full frames of video at an increased scan rate to simulate the exposure duration of a motion picture camera shutter. Then, the present invention converts these non-interlaced video images from analog to digital data. The present invention then separates the odd and even number scan lines from the data and writes this data to two of the three memory blanks. Then, the present invention reads memory blanks in a predetermined order. The digital artifacts, which simulate the grain of the film are then combined with the image data. The resulting data is then converted into a normal interlaced video signal. The description that follows will refer to a NTSC TV system. Whether this present invention will work within PAL, SECAM or the various HDTV systems that are used or have been developed around the world, speeds, frequencies, number of horizontal lines, number of pixels per line, memory requirements and frame rates they would be modified to accommodate proper synchronization and performance within the appropriate television system. This detailed description relates to the operation of the present invention within a black and white video system of an NTSC. In a color system, this invention operates on a video signal (s) before the color coding process. Therefore, it will be apparent to a person skilled in the art that most of the circuits described would be duplicated three times to accommodate the separate red, green and blue video signals. In a color system, all control and clock signals would be synchronous in time and phase between the data paths and the red, green, and blue video signals.

The input format of the video signal that goes into the present invention requires that it be digitized and stored very quickly. The output format of the stored video data requires a slower conversion. The inherent characteristics of this present invention need different input and output data regimes. The high-speed requirements of the input stage of the present invention make it more feasible to make a large amount of the data alterations to a slower output stage of the present invention. This becomes apparent taking into account the following volume and data regimes that pass through the present invention. In the NTSC versions of color or black and white, the input signal enters the present invention as a non-interlaced video frame. A complete black and white video frame is digitized and stored in memory in less than 16.7 milliseconds. Each frame contains 525 horizontal scan lines, each consisting of 756 pixels. A total of 395,850 data samples can be digitized and stored within each digitization period of 16.7 milliseconds. The digitization regime for non-interlaced input video sampling is graded at 28.63636 MHz. This digitization regime is derived by multiplying the frequency of the NTSC color subcarrier by eight. In order to achieve the NTSC standards, the original non-interlaced signal must finally be sent by means of the present invention as two interlaced fields. The first field of each frame consists of the odd number horizontal scan lines. The second field consists of the odd number horizontal scan lines. Each of these two fields contains approximately 197,925 samples of the original digitized table. However, of the original 525 horizontal lines that make up the table, approximately 486 horizontal lines are the area of the active image. The remaining lines in an NTSC system are used for synchronization purposes. By storing only the area of the active image, the storage requirements of the present invention are reduced from 262 horizontal lines to 243 horizontal lines per field. Each line of a field is addressed by an 8-bit digital address. Each pixel within each line is addressed with a 10-bit digital address. Each field of the active image area can be stored in a 256K memory device by 10 bits. The non-NTSC and high definition versions of the present invention will require more memory per field. The preferred embodiment of the present invention comprises an image forming element, an analog conditioning circuit, an analog-to-digital converter, a memory circuit, a post-conditioning circuit, a digital-to-analog converter and a synchronization and control circuit. . The method of the present invention creates video outputs that mimic the appearance of a motion picture film, wherein an image is captured and converted into a non-interlaced analog signal comprising the steps of converting the analog signal into a digital representation, separating the representation digital in odd and even number scan lines and store the separate digital representation in a plurality of memory blank spaces, remove the separate digital representations of the plurality of memory blank spaces in a predetermined manner, add grain to the digital representations and convert the digital representation into an interlaced analog signal. The present invention is not limited to any specific input or output standard, including but not limited to the standards of NTSC, SECAM, PAL, PAL-M and HDTV (High Definition Television). Figure 1 shows the manner in which the images are captured or recorded by a motion picture film camera and with a conventional prior art video camera, during a second time interval. Figure 2 shows the manner in which the film shot at 24 frames per second is transferred to 60 video fields per second with the methodology of the prior art which is known as the 3-2 conversion. Specifically, in NTSC's color television standards there are actually 59.94 video fields per second or 29.97 video frames per second that are rounded up to 60 and 30, respectively. Figure 3 shows a similar conversion process, where the film is filmed at an increased rate of 30 images per second. Since the 30 images per second of the movie are transferred to 30 video frames (60 fields) the transfer is referred to as one to one since each image of the film yields a complete video frame. This is also known in the prior art. Figure 4 shows a total view of the elements of the present invention. The interrelation of these elements is discussed in the following paragraphs. A conventional image forming element 401 is shown that provides 60 frames per second of non-interlaced video. The signal 501 is a non-interlaced video signal, of 60 frames per second of a volt. The signal 701 is the composite suppression of the image forming element to indicate the blanking intervals between the horizontal and vertical traces. The signal 710 is the horizontal driving signal of the image forming element. Signal 753 is the vertical driving signal. An analog signal conditioning circuit 402 is shown as is the analog-to-digital converter 403 ("ADC"). The synchronization and control circuit 404 is provided as well as the memory circuit 405. The post-conditioning circuit 406 is shown as well as the digital-to-analog converter 407. Finally, the interlaced video output 408 is shown where the video output connection provides the 30 normal interlaced video frames per second output. The step of converting an analog signal into a digital representation is achieved through the use of the conditioning circuit and the use of ADC as described with reference to Figures 5 and 6. Figure 5 shows a functional diagram of the conditioning circuit analog signal (corresponding to Fig. 4, circuit 402) used to prepare the interlaced input video for analog-to-digital conversion. The signal conditioning functions include a direct current / video reset buffer that sets the input analog video signal so that the image suppression equals 0 unit of the converter. The conditioning circuit of. The signals will also amplify the fixed video signal to use the full dynamic scale of the selected analog to digital converter and to compensate for the inherent loss of the low pass filter. The gain depends on the specific requirements of the selected analog-to-digital converter and the selected low-pass filter. The signal conditioning circuit of the present invention includes a low-pass, anti-rough 12 MHz filter 504 to prevent signals above the Nyquist frequency of 14.32 MHz from appearing as unwanted artifacts in the digitized signal. In Figure 5, a video signal 501 from a non-interlaced video source of 60 frames per second, such as a video imaging camera is supported to a high impedance / low impedance switch 502 for impedance equalization. The output is passed to the video amplifier 503 which provides a gain of 2. The resulting signal is supported in a low-pass filter of 12 MHz that limits the signal to less than the Nyquist frequency of half the digital conversion rate required. The output of the filtered signal from the low pass filter 504 is supported in another amplifier 505 that compensates for the loss caused by the low pass filter. The signal 508 CBLANK is a composite video suppression that is provided by the synchronization control circuit 404 (see Figure 7, output 702). The signal 508 is admitted to the amplifier 509 which reverses the signal to equal the JFET switch 510. A direct current voltage reference signal 511 of 1.41 is then provided. The signal 511 is inverted by the inverter 512. The inverter signal 512 is admitted to an driving amplifier 513 and is also sent as the signal 515. The amplifier 513 is used to drive the JFET switch 510. The JFET switch 510 uses the signal 517 to produce and interrupt the connection between the signals 516 and 518. The output of the amplifier 505 after it has been restored to the necessary level and the signal 518 is admitted in a resistance network sum circuit 506. to set the suppression portion of the video signal 501 to the reference voltage. The output of the circuit 506 is admitted to the amplifier 507, a 75 ohm impeller with a gain of 2. The driving amplifier 507 sends the signal 514, a video conditioned signal for analog-to-digital conversion subsequent Figure 6 shows a functional diagram of the analog-to-digital converter circuit used to convert the conditioned non-interlaced input video into a digital format. It uses a high-speed 10-bit bipolar analog-to-digital converter 606 (ADC). The conversion rate selected for an NTSC system is 28.6363 MHz. This sampling frequency was selected to be 8 times greater than the frequency of the color subcarrier used in NTSC television (3.57954 MHz). Although it is known in the art how to digitize the video to 4 times the frequency of the color subcarrier, the present invention uses a multiplier of 8, since the present invention operates in a non-normal mode that admits the video to the ADC circuit at a rate of 60 frames per second as opposed to the normal NTSC rate of 30 frames per second. . The present invention employs a 10-bit analog-to-digital and digital-to-analog data path. 10 bits yield up to 1024 steps from black to white. It would be possible to construct the present invention with an 8-bit data path, however, this would yield a maximum of only 256 steps from black to white.

The ADC pixel clock is engaged in horizontal synchronization. ADC will not be converted during vertical synchronization, horizontal synchronization and the suppression interval of the non-interlaced input video signal. The ADC conversion is controlled by the synchronization and control circuit 404, which is shown in more detail in Figure 7. As shown in Figure 6, the conditioned video signal 601 (corresponding to the signal 514 in the Figure 5) is supported to a terminating resistor 605 of 754 ohms. Input 603 is the negative voltage reference (corresponding to signal 515 in Figure 5) and is passed to a precision voltage reference circuit 607 that generates a reference point output as the set of signals 613. The signal 609 terminated is the analog input signal to the analog-to-digital converter 606 ("ADC"). Signal 602 (corresponding to signal 703 in Figure 7) provides ADC 606 conversion pulses. ADC 606 takes the analog input signal 609 and uses the encoding signal 602 and the set 613 of voltage reference signals to generate the digital video data 604 and the overflow signal 612. The overflow indicator 608 provides the operator with an indicator to adjust the target level by adjusting the gain of the amplifier 505 in Figure 5.

Figure 7 shows the synchronization and control circuit 404 which controls the time of the present invention from the input to the output. This includes a master 719 clock. The synchronization control signals are derived from the master clock 719 and the selection input switches so that they will be described below. The synchronization and control circuit is generally described below with detailed reference to Figure 7 which is provided after the general description. The master clock 719 and the horizontal synchronization of the video signal are locked in phase. This ensures that the pixels of each video scan line are aligned vertically, eliminating horizontal oscillation within the video frame. To ensure proper phase locking, horizontal synchronization is derived from master clock 719. The synchronization and control circuit 404 may have two digital inputs selected by the user. The inputs are the "freeze frame" selection signal and the "24/30" images per second of the selection signal. The operator selection of the frozen frame mode causes the next video frame that occurs to be retained in the memory and displayed until the "frozen frame" mode is changed. The "24/30" mode selector switch 746 determines the order in which the video input data bus is written to the three field memory groups (856. 857 and 858 of Figure 8) and that they are read from. these memory groups to the video output data bus. The read and write operations of the memory are simultaneous. The data on the video input data bus is written from two of the memory groups, while the video output bus is being read from the third memory group. These three groups of high-speed video memory are shown in Figure 8. The selection of the operator of the "30" mode causes the present invention to send an interlaced video frame that is derived from each other non-interlaced frame of the video-forming device. CCD images. The "30" mode simulates the "look" of movement as captured in a conventional motion picture camera operating at 30 frames per second (see Figure 3). The synchronization and control signals for mode "30" provide a sequence of the input and output of the three field memory groups as a circular buffer. For any given image, one of the three field memory groups will be used to store the horizontal scan lines of odd number. One of the two remaining field memory groups will be used to store the odd-numbered horizontal lines that make up a complete video frame. An effort has been made to sequence the three memory groups so that the number of read and write operations for each of the three memory groups is balanced. This technique distributes better the dissipation of the energy between the groups of memory. Table 1 of Figure 11 gives details of the memory synchronization project for operation in "30" mode. This synchronization project is repeated in the seventh field. Even when the third memory group is necessary only for the "24" mode, it is used in the "30" mode to equally distribute the heat dissipation of the memory circuit. The selection of the operator of mode "24" causes the present invention to simulate the 3-2 conversion (see Figure 2) required to transfer the motion picture film, shot at 24 frames per second to a video. The method of reading and writing the memory as described above in "30" mode, is used in the "24" mode, but the sequence of reading and writing is altered. In "24" mode, during the output of each other video frame, one of the field memory groups is read twice. It is important that the order of even and odd video fields be preserved to avoid vertical oscillation and maintain a full vertical resolution. The 24 fps memory synchronization project repeats itself in the 11th frame. Table 2 of Figure 11 details the memory synchronization project for operation in "24" mode. In a color video system, synchronization control signals would be common for all three video channels (red, green and blue). This provides accurate synchronization between the three parallel video channels. As shown in Figure 7, the input signal 701 (see also Figure 4) comprises the suppression from the non-interlaced video source which is converted to a digital signal by the 75 ohm buffer 718. The output of the buffer 718 is the composite suppression signal of the video source or CBLNK signal 712. The input signal 712 is the external horizontal drive. The signal 712 is converted into a digital logic level signal 742 by the 75 ohms buffer 716. The input signal 713 is the external vertical impussion. The signal 713 is converted to a digital logic level signal 743 by means of the 75 ohms buffer 717. The operator interface 714 controls the frozen frame control logic signal 744. The operator interface 715 provides the operator with a choice between film simulation modes of 24 and 30 frames per second. The total system is controlled by master clock 719. The frequency of the master clock is variable and controlled by the signal 740. The signal 740 is generated by the phase-locked circuit 720. The phase-locked circuit 720 generates a control voltage with a phase comparison of the clock signal 741 and the horizontal drive signal 742. The master clock 719 also generates a write clock signal 703 by logically placing the clock signal 741 in the "AND" circuit with a suppression signal 712 composed of the video source and also logically placing with the signal 744 in the AND circuit. of operator interface 714. The clock signal 705 read is half the internal clock frequency. It is derived by dividing the signal 742 by two and by logically placing the result in the AND circuit with the composite suppression signal 708. The master influence generator circuit 721 combines the horizontal driving signal 742, and the clock signal 741 to generate the horizontal interlaced video driver 748, the vertical system driver 749, the interlaced mixed video sync 707, the composite video suppression interleaved 708, vertical synchronization 751 and field indicator 752, and horizontal camera impeller 747. The camera horizontal impeller signal 747 is twice the frequency of the horizontal impeller 748 due to the frame rate of 60 frames per second of the video source. The state circuit 722 uses the vertical synchronization 751, the logic and field indicator 752. The state circuit 722 also uses the frozen frame control logic signal 744 and the 24/30 frame selection signal 746 to generate the state bus signal 709 in order to control the memory sequence based on the displayed frames in Figure 11. The signal 746 controls which state box to use. Signal 752 is used to synchronize the beginning of the state sequence and compared to the field bit (odd or even reading) that is coded in the state sequence to ensure that the correct field is read. The signal 744 stops and starts the sequence. The signal 751 controls the synchronization of the sequence. The state circuit 722 establishes the status bus 709 during the vertical blanking interval. Because the state selection occurs during the horizontal intervals, this slow rate allows a microprocessor, for example, to be used for the state circuit. The write address counter 723 combines the write clock signal 703, the horizontal camera driver 747 and the vertical driver 749 of the system to generate a write address 704. The write address 704 consists of address bits of 10 pixels per line, 1 bit to specify odd or even fields, and 8 bits for the address of the line number. Accordingly, the write address counter 723 is a 19 bit counter. Each write clock signal 713 increments the lower 10 bit section of the write address counter 723. Each horizontal booster pulse 747 of the chamber clears the lower 10-bit section of the write address counter 723 and embeds the upper 9 bits of the write address counter 723. The vertical impeller 749 of the system clears both sections of the script address counter 723, all of 19 bits. The read address counter 724 combines the read clock 705, the horizontal interleaved impeller 748 and the vertical impeller 749 of the system to generate a read address 706. The read address 706 consists of address bits 10 pixels per line and 8 bits to address the line number. Accordingly, the read address counter 724 is an 18 bit counter. Each read clock signal 705 increases the lower 10-bit section of the read address counter 724. Each interlaced horizontal impeller pulse 748 clears the lower 10-bit section of the read address counter 724 and increments the 8 bits of the read address counter 724. The vertical impeller 749 of the system clears both sections of the counter, all of 18 bits. A 75 ohm impeller 725 amplifies the camera's horizontal signal 747 and sends the signal 710. The impeller 726 amplifies the mixed synchronization signal 707 and outputs the signal 711. The impeller 727 amplifies the vertical drive signal 749 and sends the signal 753. Figure 8 shows three groups of random access memory for storing the digitized video data. This memory is necessary to convert the non-interlaced input video image into an interlaced output signal with the selected effective framing rate (24 fps, 30 fps or the frozen frame). In Figure 8, the memory subsystems of the present invention include the address multiplexer and the memory control circuit. These circuits decide which of the three groups of high-speed field memory will save the input data of the analog-to-digital converter 403. This circuit decides which of these groups of field memeoria will be sent to the converter 407 from disgital to analog. Also, the address multiplexer and the memory control circuit which read and write memory addresses should be sent to the appropriate memory group. The high-speed field memory groups of the present invention consist of three identical memory groups, each of which is used to store a field of the video data. Based on the speed requirements for the present invention, the memory write cycle must be less than 35 nseconds. The minimum size requirements for a 10-bit NTSC system is 256K X 10 bits per field memory group. A total of three field memory groups are used in a black and white camera. A color version of the present invention employs nine field memory groups. In Figure 8, bus 804 contains the status bus data (which corresponds to bus 709 in Figure 7). The input signal 805 is coded in the write clock (corresponding to bus 703 in Figure 7). The bus 804 and the input signal 805 are used by the memory control 810 to generate signals in the memory control. The buses 850, 851, 852, of contol determine whether a group of read memory is capacitated, one of writing is capacitated or incapacitated or provides the clock rate. The address bus selectors 811, 814 and 817, one for each memory group, are used to select either the write address bus 802 or the read address bus 803 and generate addresses for the buses 853, 854 and Address 855 again one for each memory group. The memory groups 812, 815 and 818 provide a 10-bit high-speed digital memory and use the control buses 850, 851 and 852 and the address buses 853, 854 and 855 to store and retrieve the digitized video data to through the buses 856, 857 and 858 of bidirectional video data. In memory, the data bus selectors 813, 816 and 819 that use the information of the control buses 850, 851 and 852 to write the data to the memory from the video data bus 801 (correspondingly to bus 604 in Figure 6) through buses 856, 857 and 858 of bidirectional video data to memory groups 812, 815 and 818. During the reading of the memory, the data bus selectors 813, 816 and 819 use the information from the control buses 850, 851 and 852 to move the data from the memory groups 812, 815 and 818 through the buses of data 856, 857 and 858 of birectional video to the bus 806 of digital video data output. Otherwise, the data bus selectors 813, 816 and 819 provide no operation in the memory. These salient features of the memory control 810 ensure that only one group is read and no more than one group is written at any given time (see Figure 11, tables 1 and 2), disabling unused memory groups and causing the digital video data to be written into memory. The step of separating the digital representation of the video image in order to scan odd and even numbers and store the separate digital representations in a plurality of memory groups is achieved through the use of the synchronization and control circuit 404 and the circuit 405 of memory as described with respect to Figures 7 and 8, while the step of removing the separate digital representations of the plurality of memory groups in a predetermined manner is accomplished through these same circuits and is described with respect to these same in Figures 7 and 8. Figure 11 describes the manner in which the reading and writing cycles occur to simulate a film shot at 30 frames per second (fps) and 24 frames per second. Figure 9 shows a functional diagram of the post-conditioning circuit 406 of the present invention for the addition of simulated film gain and other effects. The main use of this data port is to digitally introduce the simulated film grain into the video data stream. In Figure 9, the input status bus 904 (which corresponds to the bus 709 in Figure 7) and the composite suppression signal 913 (corresponding to the signal 708 in Figure 7) are used by the number generator 910 randomly to synchronize the generation and placement of a random starting address for each frame on the 950 bus of pre-graduated address. The random number, for example, can be generated by a microprocessor. The number is generated between frames, as determined by the status bus 904 and synchronized by the composite blanking signal 903. The pre-graduate counter 911 uses the read clock signal 902 (corresponding to the signal 705 in Figure 7), the composite suppression signal 913 and the pre-graduated address bus 950 to generate and place an address on the address bus 951 EPROM. The address is generated by first adjusting the address to the value on the pre-graduated address bus 950 to a composite blanking 903 and then incrementing the addresses by reading clock 902 for each output pixel in the frame. An EPROM 912 is preprogrammed with the data representing a very large field of two-dimensional artifacts that simulate the grain of the film. The very large field is more than three times larger than a pixel count of an interlaced video frame. In order to obtain sufficient size and speed, several EPROM can be used in parallel. The address to be read is taken from bus 951 address. The data in the address specified by the address bus 950 is sent in the bus set 952 of parallel data. The data in the parallel data buses 952 is reduced to a 4-bit data on the digital grain bus 953 using the lower address bits of the EPROM address bus 951. The intensity of the grain is specified by the selector 905 of intensity and is sent on the bus 954. The digital summation circuit 914 adds from 0 to 4 bits, as determined by the bus 954 of the digital grain data from the bus 953 to the digital video data on bus 901 (which corresponds to bus 806 in Figure 8) and sends the result on a bus 906 digital video data output. The grain intensity is determined by the number of bits of the degital grain data from bus 953 that is added. For example, the operator selects the grain intensity with a multi-position rotary switch of the selector 905. The step of adding the grain to the digital representations is achieved through the use of the post-conditioning circuit 406, as described with respect to to Figure 9. Figure 10 shows the digital-to-analog video converter 407 (DAC) of the present invention that converts the post-conditioned video data stream of Figure 9 into a conventional video signal, monochromatic, analog composite. In the black and white system, the DAC output represents the luminance signal. In a color system, the three DAC output represents the individual red, green and blue video signals before the color coding process. In FIGURE 10, the voltage reference 1005 generates the signal 1048 to be used as a reference for the specific digital-to-analog converter to be used. The full-scale setting 1006 sends the signal 1049 which is used to adjust the target level of the analog video output 1007. The digital-to-analog converter 1010 converts the digital video data into bus 1001 (which corresponds to bus 906 in FIGURE 9) into an analog video signal 1050. The digital-to-analog converter 1010 converts the data to bus 1001 when it receives signals by reading clock 1002 (corresponding to signal 705 in FIGURE 7). The voltage reference signal 1048 and the full scale adjustment signal 1049 are used to determine the full scale value of the analog output 1050 of the digital-to-analog converter 1010. The digital-to-analog converter 1010 inserts the suppression level when it receives signals from the complete suppression 1003 (which corresponds to the signal 708 in FIGURE 7) and inserts a video synchronization pulse when it receives signals through the synchronization 1004 mixed (which corresponds to signal 707 in FIGURE 7). The analog signal 1050 is bandlimited by the low pass filter 1011 and is sent as a 1051 analog video signal. The analog video signal 1051 is amplified by the 75 ohm impeller 1012 and sent as a conventional interlaced analog video input 1007. The step of converting the digital representation into an interlaced analog signal is achieved through the use of the digital-to-analog converter 407, as described with respect to FIGURE 10. Having now described the invention in detail as required by the patent statutes , those skilled in the art will recognize that modifications may be made to the embodiments described herein for specific applications. These modifications are within the scope and spirit of the invention as defined in the following claims.

Claims (6)

CLAIMS:

1. A video camera comprising: (a) a non-interlaced video signal image forming element; (b) an analog conditioning circuit for amplifying and limiting in band a non-interlaced video signal generated by the image forming element of the non-interlaced video signal; (c) an analog-to-digital converter for converting the non-interlaced video signal into a digitally-represented signal; (d) a memory circuit comprising a plurality of memory groups for storing the digitally represented signal; (e) a post-conditioning circuit for introducing the grain to the digitally represented signal; (f) a digital-to-analog converter for converting the digitally represented signal into an interlaced signal; and (g) a synchronization and control circuit for synchronizing the conversion of the non-interlaced video signal into the digitally-displayed signal and the conversion of the digitally-represented signal into an interlaced signal for storing and removing the digitally-displayed signal to and from the memory circuit, and to synchronize the grain addition.

2. The invention in accordance with the claim 1, wherein the post-conditioning circuit for introducing the grain to the digitally represented signal comprises a means for adding a selective adjustable amount of two-dimensional artifacts. The invention according to claim 1, wherein the non-interlaced video signal image forming element comprises a double speed scanner. 4. A method for creating video outputs that mimic the appearance of a motion picture where an image is captured and converted into a non-interlaced analog signal, the method comprising the steps of: (a) converting the analog signal into a digital representation; (b) separating the digital representation into odd and even number scan lines and storing the separated digital representation in a plurality of memory groups; (c) removing the separate digital representations of the plurality of memory groups in a predetermined manner; (d) add grain to digital representations; and (e) converting the digital representations into an interlaced analog signal. The invention according to claim 4, wherein the step of adding grain to the digital representations comprises synchronizing the generation and placement of a random starting or starting address for each frame in a pre-graduated address bus, increasing the addresses using a read clock signal for each output pixel in the frame, send the data to the address specified by the address bus to a set of parallel data buses, reduce the data to 4 bit data, and adjust the intensity of the grain through an intensity selector. 6. The invention according to claim 4, wherein the image is captured by a double speed scanner.