MXPA96001918A - Memo chip architecture - Google Patents

Abstract

The present invention relates to a memory chip or microplate for storing digital data, the digital data corresponds to a previously recorded audio signal and the memory chip is adapted for insertion into an associated audio player, the memory chip is characterized in that it comprises : a plurality of memory cells, each of the memory cells is individually addressable to access the data therefrom, a first means coupled to the plurality of memory cells to receive input data in series from the player associated audio, a second means coupled to the plurality of memory cells for transmitting data in series from the memory chip, the memory chip is adapted to receive DC power, ground and a clock signal from a dc deviation circuit in the audio player, where the dc energy signal and the clock signal are transferred in combination, with each other, on a single contact, the deviation circuit dc includes a deviation generator dc having a transistor polarized by a resistive divider network for producing the energy signal, a resistive diode network for passing through the energy signal and prevents leakage of the clock signal and the mixing means to mix the clock signal with the energy signal dc, wherein the bypass circuit provides a buffer between the bias generator dc and an exposed contact; of memory includes a recovery circuit, the recovery circuit has a low pass filter to recover the energy signal dc and a current blocking means dc coupled to the transistor amplifier to recover the signal

Description

CHIP MEMORY ARCHITECTURE 4 FIELD PS TA INVENTION The present invention relates to the organization of components in a digital recording medium, and more particularly to a single semiconductor storage medium for addressable storage and retrieval of reproducible prerecorded audio signals.

ANI? SUGGESTIONS OF THE INVENTION Currently there are many recording media for storing recorded music previously addressed to the consumer and other audio applications. These media include CD ROM (Read Only Memory for Compact Disk), DAT (Digital Audio Tape) and the traditional magnetic cassette audio tape, just to name a few. Of the above technologies, the compact disc format has increasingly increased its popularity and has gained consumer acceptance due to the high sound quality of the digitally stored audio signal, as well as its ease of use. use.

However, CDs and other formats have some significant disadvantages. For one, compact discs usually include the ability to record the content of information stored on the disc before selection in a player. In other words, in order to obtain any information regarding the content of a particular music selection, the selection must first be in some way that can be accessed manually in the player. In the alternative, CD players can be manually programmed to play certain selections based on user input. However, in any circumstance there is no way to automatically search and play music by category, for example, by artist, type of music, etc., unless the user has prior knowledge regarding the selection. In addition, compact discs or optical digital discs, as they are sometimes mentioned, require high-precision mechanical drive unit systems and precise servo-controllers that are used in conjunction with solid-state laser systems for the operation of a digital player. CD. Thus, the fact that the disk must rotate at a constant linear velocity during its reproduction requires a substantial number of precisely manufactured moveable mechanical parts which tend to fall outside the tolerance of the design due to wear. These and other factors tend to limit the solids and portable capacity of current CD systems. In addition, because the size of the CDs and the need to protect their recording surfaces, the ability to transport more conveniently some CDs is also a limiting factor.

DESCRIPTION D TAT.T.ADA OF THE INVENTION The present invention is directed to a memory device for digital storage of pre-recorded or pre-recorded audio data or signals and other digitally stored data related thereto. The memory device includes components for routing, retrieval and automatic search of stored data. In an exemplary embodiment, an array of memory cells for digitally recorded audio signal storage is contained within a plastic package of modest size. In the preferred embodiment, the memory cells are constituted of read-only memory (ROM). Each of the memory cells is individually addressable on a common parallel address link and the data is read and / or written on the parallel data link. The data is transmitted to and from the device by means of serial interconnection with a solid state audio player. The deviation registers within the memory device are coupled to the serial interconnect to transmit serial data and to receive data in series from the audio player. The data buffers are interposed between the common address link, the common data link and the respective deviation registers for storing data to be placed on the common address link and for receiving data from the common link. In accordance with one aspect of the invention, a series of capacitive plates is included to provide an interconnection with less contact between the memory device and the associated solid-state audio player.

BRIEF DESCRIPTION OF THE FIGURES For a better understanding of the present invention, reference may be made to the following description of the exemplary embodiments thereof, considered together with the accompanying drawings, in which: Figure 1A shows a perspective view of a preferred embodiment of the package of the chip or memory chip of the present invention; Figure IB shows a plan view for a portion below the memory chip of the present invention; Figure 2 shows a preferred embodiment of the internal circuits for the memory chip of the present invention; Figure 3 shows a preferred embodiment for an interconnection used with the memory of the present invention; and Figure 4 shows a preferred embodiment of a deviation circuit in an audio player used for mixing in the clock signal and the recovery circuit in the music chip used to recover each of the signals.

FIPTTP ^ T ^ P TftHí ^ A r > Tfíff PTfítt.tn < ? With reference to Figure 1A, a preferred embodiment of a chip package for the memory chip of the present invention, hereinafter referred to as a music chip 10, is shown. The music chip 10 is essentially a memory component which is adapted to be received in a companion solid state audio player for playing music contained in the memory. The physical characteristics of the chip 10 are essentially that it is a flat rectangular device having dimensions of approximately 6.4 x 2.3 x 0.6 cm (2.5"x 1.125" x 0.25") and housed in rugged ABS plastic (acrylic butyl styrene) or other similar material. The music chip device of relatively small size has significant advantages over compact discs and other media with respect to its transport and storage capacity. The memory and interconnection circuits in chip 10 are embedded within the package, as will be explained. The music chip 10, as will be understood, is designed for the storage of previously recorded audio, specifically music. A window 12 of the graphic is included in the upper surface 14 of the chip for display of illustrations and other labels associated with pre-recorded music sold at retail. Therefore, the graphic window 12 will contain information similar in scope to that found on the front of a compact disk or a cassette tape package. A front portion of the chip 10, at an opposite end to that of the window 12 of the graph includes a cylindrical recess 16 that extends completely through the planar body portion of the chip. The recess 16 presents a convenient way to transport one or more of the chips insofar as the devices can be inserted or threaded through the recess retained with a key chain or otherwise. On both sides of the chip 10, close to the window 12 of the graph, metal contacts 18, 19 are placed to supply power, grounding and clock signals to the chip circuits. A notch 20 to 45 degrees located in the corner of the upper right part of the chip 10, with the purpose of conveniently designating the rear end 22 of the chip as an area which must be inserted first into the audio player. The notch 20 also differentiates the face-up insertion, as compared to the face-down insertion of the chip 10. With reference to FIG. IB, a bottom view of the chip 10 is shown. A group of four capacitive plates 23-26 are embedded in it. bottom side 28 of the chip for data transfer between the chip and the player. Using the capacitive plates 23-26 embedded together with the material of the rugged plastic housing makes the device extremely tolerant to most of any type of handling. In addition, due to the unique packaging and associated circuit design, many problems common to other types of chips such as electrostatic discharge (ESD) are minimized to a large extent. The memory of the music chip 10, as explained, will contain pre-recorded music or other similar audio content, wherein the music is stored in a compressed digital format. The compression is performed according to an audio coding algorithm, a detailed discussion of which is not required for the compression of the present invention. With reference to Figure 2, a preferred representation for the configuration of the internal circuitry of the music chip 10 of the present invention is shown. As mentioned, the music chip 10 is adapted to be received in a solid state audio player. Figure 2 shows the music chip 10 as it is coupled to such an audio player 30. It will be understood that the audio player 30 will be any of many devices, for example portable or stationary, devices which are adapted to access, receive and reproduce digital audio signals stored in the memory of a music chip 10. As shown, the audio player 30 includes a digital signal processor 32 (DSP) for decoding the data stored digitally in the music chip memory. A data line 34 is coupled from the DSP 32 to a data deviation register 36 in the player 30. An address line 38 and a bit I / O line 40 are similarly coupled from the DSP to a data logger 42. address deviation. Address lines, I / O bits and data are sent and received to and from the diversion recorders 26, 42 which in turn send and receive data to and from the music chip 10. It will be understood that the address lines, I / O bits and data lines can be in a common link format to accommodate parallel data transfer. In this case, the diversion registers 36, 42 will necessarily be adapted to receive the parallel data and then the same output serially, or alternatively, to receive data in series and be able to output data in parallel. In any case, the data is then serially transferred to and from the deviation registers 36, 42 of the audio player 30 via capacitive coupling plates 43-46 which correspond to the capacitive plates 23-46 of the music chip 10. . The corresponding plates are aligned when the music chip 10 is inserted into the audio player 30 which generates a plurality of capacitors which form a capacitively coupled interface. Referring again to Figure 2, it can be seen that the structure of the internal memory 50 of the music chip 10 appears similar in nature to that of, for example, an instantaneous EEPROM. An array of memory cells 50 is included therein, wherein each memory cell 50 is individually addressable via a common link 52 of parallel address. Each of the memory cells 50 is read from (or written to, if applicable) a common link 54 of parallel data. The memory for the music chip will typically be a read-only memory (ROM), in which the pre-recorded digital audio will be represented in a mask which is copied at the time of manufacture and which exactly duplicates the audio of a master tape encoded for which it has been reproduced. As an alternative, the music chip memory can also be a type of programmable ROM (PROM), in which each of the memory cells is written only once in order to store audio blocks. As another alternative, the memory can also be a non-volatile random access memory (RAM) device, for example, an INSTANT RAM, where both read and write operations can be carried out. However, in the case of pre-recorded audio, writing operations to the music chip will normally never be necessary once the audio has been recorded, therefore, the additional production costs associated with RAM do not seem justified. Within the shown embodiment of the music chip 10 in FIG. 2, a common link 52 of parallel address and a common data link 54 are coupled to each of the memory cells 50. Of course, it will be understood that the common address link can be coupled to the memory through the decoder circuits 51, which are known in the art. As shown, the common address link 52 and the common data link 54 are unidirectional common links and the indicated arrows 53 are representative of the data flow direction. That is, the addresses of the audio player are accepted on the music chip to access specific memory locations, while the data of the memory cells, after they have been accessed, come out on the link common 54 data. However, it will be understood that the common data link, in particular, can be manufactured to be bidirectional, depending on the memory technology used within the chip. As can be seen in Figure 2, the address common link 52 is coupled to a buffer 56 and in a manner similar to the common data link 54 is coupled to a data buffer 58. The address buffer 56 and the data buffer 58 in turn are coupled to an associated address offset register 60 and a data offset register 62, respectively, on the music chip 10. The function of the address buffer 56 is to receive from the address deviation register 60, in which the address data can be accessed in parallel, and output these addresses on the common link 52 of parallel address. Conversely, the data buffer 56 receives parallel data from the common data link 54 and temporarily stores the data of the parallel load in the data offset register 62. The addresses and data are serially transferred to and from the deviation registers 60, 62 of the music chip by means of the capacitive plates 23-26 which align with the capacitive plates 43-46 of the audio player 30. The transfer of address information and data to and from chip 10 to audio player 30 via capacitive plates 23-26 provides a significant advantage over other memory chip packaging since the need for electrical contacts is avoided exposed. The conductive plates or electrodes have outer dielectric surfaces both on the chip 10 and on the audio player 30 and form an electrical interface when each plate on the chip is aligned in close proximity with the corresponding plate on the player. When the chip 10 is in place within the audio player, the routing and data information is transferred reliably. This remains valid even after some time of use, since for the data transfer circuits, there are no exposed metal surfaces that corrode or in which particles can be collected. In addition, the potential for damage from electrostatic discharges to the electronic components within the chip is minimized since an insulator in the form of a dielectric is provided between the chip conductors and any source from which a discharge may occur. It will be understood that other types of interconnections can also be used, for example metal contacts, however capacitive interconnections are preferred for the reasons described. With reference to Figure 3, a more detailed illustration of the capacitive interconnection found within the music chip 10 and the audio player 30 is shown. The capacitive plates 23, 24 are coupled to the data receiver circuit consisting of a differential amplifier 70 adapted to receive data from the corresponding capacitive plates 43, 44, the corresponding capacitive plates 43, 44 are coupled to the differential drive or unit circuits 80 in the player 30. The output of the differential amplifier 70 is coupled to the input of the deviation register 60 which receives the addressing information. in series as explained with reference to Figure 2. A data output drive or activation circuit, comprising drive amplifiers 72, 74, is coupled to the data offset register 62, and receives the serial data from the same to differentially activate the capacitive plates 25, 26.

The capacitive plates 25, 26 coupled to the activation circuit are then capacitively coupled to the corresponding plates 45, 46 in the player when the chip is inserted, in which the data is received in a differential amplifier 81 and received in the recorder 36. of deviation. The activation amplifiers 72, 74 convert the serial data of the data chip recorder 62 of the music chip which is of one polarity, to a differential polarity so that for each transition of a signal from the chip, one of the activators becomes positive while the other becomes negative. Therefore, two of the capacitive plates on the chip are used for data entry (or addressing) while the other two plates are used for data output. As can be seen, a mirror image of the same scheme is used for player 30. The differential data transfer scheme ensures a more reliable transfer of information since two data terminals are active to indicate a transition from one state to another . In addition, the hysteresis accumulates within the data received by the circuits to avoid false activation by noise from the outside.

As explained, the metallic contacts 18, 19 made, for example, of copper coated with nickel are located on both sides of the chip 10 to provide power, grounding and clock signals or synchronization to the internal circuits thereof. Although metal contacts 18, 19 are provided on the chip, the contacts are mounted closely to the body of the chip so that they do not protrude a great distance therefrom. This, in combination with a surge protection coupled to the circuit lines running from the contacts, will reduce the possibility of ESD damage. In a preferred embodiment of the invention, only two contacts are used to provide power (3.3 direct current voltage) grounding and clock signals, where the clock signal is transmitted along with one of the power connections. This is done to reduce the susceptibility to ESD by minimizing the exposed contact area, as well as to minimize the effects of corrosion on exposed metal surfaces. Referring to Figure 4, preferred embodiments of a DC offset circuit 90 and a clock recovery circuit 92 used in the audio player 30 and the music chip 10, respectively, are shown to transmit the energy and signals clock together from a contact. Deviation circuit 90 of de includes transistor TI (MOSFET) which is deflected by means of the resistive divider network constituted of resistors R1 and R2, and functions to provide a stable deviation for the voltage output VDD of the generator 30 of Audio. The deviation signal from the transistor TI enters a resistive diode network 91 which prevents the backward leakage of the clock signal (OSO in the power circuit.) The DI diode is deflected forward to pass the deviation signal. A relatively large value is assigned to R3, for example one megaohm so that it is able to pass only a minimum feedback current The clock signal (OSO is added or mixed with the deviation signal at junction Jl in that the clock signal is effectively carried on the carrier of, as shown, In addition to providing a stable deviation value, the deviation circuit of FIG. 4 also generates a buffer between the power circuits and the exposed contact The values of Rl and R2 are chosen according to the desired deviation, in which typically Rl is selected to be much greater than R2.The combination signal is transferred from the reprodu 30 audio signal to the music chip through one of the metal contacts 18, 19, in which the clock is extracted from the power signal by means of a clock voltage recovery circuit / voltage 92 direct (VDC). The VDC recovery circuit is comprised of a low pass filter 94 that includes Rll and Cll. Rll and Cll integrate the input signal with respect to time to produce an ac signal, in which VDC appears in the output terminal 95 of the low pass filter 94. The clock recovery circuit 96 includes a transistor T2 amplifier which is activated in the mode of improvement or abatement by the clock signal of. The capacitor C21 blocks the portion of of the combination signal and the extracted clock signal appears in an output terminal 97 which is coupled to the drain of the transistor T2. Depending on the clock frequency used, Rll, Cll and RD, RS are chosen so that RD is much greater than RS. It will be understood that in the alternative, three contacts can be provided for the transfer of each of the signals individually. As is known in the art, the data transfer is coordinated through the music chip 10 and the audio player by means of the clock and other corresponding signals which are provided from the DSP. In operation, the present invention of the music chip 10 operates as follows. An address request is provided from the DSP 32 of the audio player 30 to read the data content at a memory location specific to the music chip. The address information is transferred to the address deviation register 42 of the audio player in which it is transferred on the capacitive interconnection plates of the audio player and the chip, respectively. The address is received in the data reception circuit of the music chip 10 in which it is converted to a standard serial data sequence and then stored in the address deviation register 60. In accordance with the clock cycles and the control signals of the DSP 32, the address information from the address deviation register 60 is switched in the address buffer 56 in which the information is placed on the common link 54 of parallel address to access a specific memory location. Once the specific memory cell has been identified, the data is read from the memory cell and placed in the common data link 54. The data is transferred over the common data link 54 and received in parallel in the data buffer 58. The data from the data buffer 58 is then loaded into the data offset register 62 in parallel. The data loaded in the data diversion recorder 62 can then be output in series through the activating circuits over the capacitive interface when it is received in the data deviation recorder 36 of the audio player 30. The data can then be read to be processed by means of the DPS 32. In a preferred embodiment of the invention, the data transfer to and from the memory takes place at a rate of 150 KHz. Therefore, a unique architecture for digital audio storage within a semiconductor chip has been presented. The chip allows the serial transfer of data to and from the chip by means of an interconnection capacitively coupled to the audio player. The serial data is then converted and transferred into the chip by means of common address and parallel data links. The data then once again comes out serially again for decoding and processing by the audio player. From the above, it will be understood that the modalities described, with respect to the drawings, are only exemplary, and that a person skilled in the art can make variations and modifications to the modalities shown without departing from the spirit and scope of the invention. All such variations and modifications are considered to be included within the scope of the invention as defined in the appended claims. It is noted that in relation to this date, the best method known by the applicant to carry out the aforementioned invention, is the conventional one for the manufacture of the objects to which it relates. The invention having been described as above, the content of the following is claimed as property:

Claims (30)

1. A chip or memory chip for storage of digital data, the digital data corresponds to a pre-recorded audio signal and the memory chip is adapted for insertion into an associated audio player, the memory chip is characterized in that it comprises: a plurality of memory cells, each of the memory cells is individually addressable to access the data from it; first means coupled to the plurality of memory cells for receiving input data in series from the associated audio producer; and second means coupled to the plurality of memory cells for outputting data in series from the memory chip.

2. The memory chip according to claim 1, characterized in that the first means is adapted to output the input data in parallel and the second means is adapted to receive data in parallel.

3. The memory chip according to claim 2, characterized in that the memory chip includes a common parallel address link and a parallel data common link, each of the common links is coupled to the plurality of memory cells.

4. The memory chip according to claim 3, characterized in that it additionally includes: intermediate address buffer means for interconnection with the common address link, the intermediate address buffer means are adapted to temporarily store data which leaves from the first means; a data buffer means for interconnection with the common data link, the buffer means is adapted to temporarily store data that is input to the second means.

5. The memory chip according to claim 1, characterized in that it additionally comprises a plurality of capacitive plates for the input and output of data, without contact, to and from the memory chip.

6. The memory chip according to claim 5, characterized in that it additionally includes an activation circuit or output unit coupled to the second deviation register, the output activation circuit is adapted for differential data output.

7. The memory chip according to claim 5, characterized in that it also includes a data receiver circuit adapted to receive differential activated data.

8. The memory chip according to claim 1, characterized in that a memory is included within the housing, the housing includes a means for displaying labels or indicators that correspond to the pre-recorded audio signal stored on the chip.

9. The memory chip according to claim 8, characterized in that the housing includes an opening that extends completely through a portion of the chip, the opening is adapted to facilitate the transport of the memory chip.

10. The memory chip according to claim 8, characterized in that the housing is constituted by acrylic butyl styrene.

11. The memory chip according to claim 1, characterized in that the plurality of memory cells are constituted by read-only memory (ROM).

12. The memory chip according to claim 1, characterized in that the plurality of memory cells constitute a type of programmable read-only memory.

13. The memory chip according to claim 1, characterized in that the plurality of memory cells comprise a type of random access memory (RAM).

14. The memory chip according to claim 1, characterized in that it also includes means for decoding the input data received from the audio player in order to have specific access to some memory cells.

15. A semiconductor chip memory apparatus for storing pre-recorded audio signals, the memory apparatus is adapted for use with a solid state audio player, the apparatus comprising: a plurality of memory cells for storing digital data therein; an address deviation register to receive serial data corresponding to the addresses of memory locations; and a data deviation register to output the serial data read from the selected memory locations.

16. The apparatus according to claim 15, characterized in that it further includes a common parallel address link La and a parallel data common link, wherein the address deviation register is adapted to output parallel address data in the common link of address and the data deviation register is adapted to receive parallel input data from the common data link.

17. The apparatus according to claim 16, characterized in that it also includes an address buffer and a data buffer, wherein the address buffer is operative to receive address information from the address deviation register for placement in the common address link and data buffer is operative to receive data from the common data link for its introduction to the data deviation recorder.

18. The apparatus according to claim 15, characterized in that the address deviation register and the data deviation register are coupled to the audio player by means of capacitive plates.

19. The apparatus according to claim 18, characterized in that it additionally includes means for differentially transmitting data from, and for receiving data within, the memory chip apparatus.

20. The apparatus according to claim 15, characterized in that the memory chip apparatus is included within a plastic housing, the housing includes a graphic display area for the inclusion of labels belonging to the pre-recorded music.

21. The compliance apparatus of claim 15, characterized in that the housing includes a hole or recess placed in a position at the end thereof where the apparatus can be transported by means of an attached conveyor device through the orifice.

22. A recording medium for storing digital data representative of audible sounds and for cooperating with a digital audio player coupled to the recording medium through an interconnection or capacitively coupled interface, the digital audio player is operable to reproduce the audible sounds stored, the recording medium is characterized in that it comprises: at least one addressable memory component that includes a plurality of specific memory locations in which digital data is stored; decoding means responsive to address signals from the audio player to designate specific memory locations; and means sensitive to the decoding means for reading the digital data from one of the designated specific memory positions.

23. The recording medium according to claim 22, characterized in that it additionally includes means for coupling the memory component to the interconnection capacitively coupled and adapted to receive and transmit data in series.

24. The apparatus according to claim 15, characterized p > or the chip apparatus is adapted to receive power from, grounding and a clock or synchronization signal from the audio player, the apparatus additionally includes a first and second contacts adapted to be coupled with the corresponding contacts in the audio player, wherein the energy of and the clock signal are transferred in combination with each other over a single contact, the chip apparatus includes means for recovering the energy of and the clock signals.

25. The apparatus according to claim 24, characterized in that the means for recovery includes a low-pass filter for recovering the energy signal from and a means for blocking the current from being coupled to a transistor amplifier.

26. A combination of digital recording medium and audio player for reproducing digitally stored audio signals, wherein the digitally stored audio signal is encoded on the recording medium as digital data and the audio player is adapted to decode the digital data, the recording medium is characterized in that it comprises: a plurality of memory cells, each of the memory cells is individually addressable to have access to data thereof; a first means coupled to the plurality of memory cells for receiving input data in series from the audio player; second means coupled to the plurality of memory cells for outputting data in series from the recording medium; wherein the audio player comprises receivers adapted to be coupled to the second means of the recording medium to receive data in series; output means adapted to be coupled to the first means of the recording medium to output data in series to the first means; and processing means coupled to the receiving means and the output means, the processing means are adapted to decode the digital data to thereby reproduce and read the digitally stored audio signal.

27. The combination according to claim 26, characterized in that the recording means and the audio player each include: an address deviation register to receive data corresponding to the addresses of the memory locations; and a data deviation register to output the data reading from the memory locations.

28. The combination according to claim 26, characterized in that the recording medium is adapted to receive a grounding power signal and a clock signal from the audio player, the recording medium includes a first and second contacts adapted for coupling with the corresponding contacts in an audio player, wherein the clock and energy signal are transferred in combination with each other, in a single contact, the chip apparatus includes a means to recover the clock and energy signals .

29. The apparatus according to claim 28, characterized in that the means for recovering includes a low pass filter for recovering the energy signal from and a means for blocking the coupled current to an amplifying transistor.

30. The apparatus according to claim 28, characterized in that the audio player includes a means for producing a deviation signal of and a mixing means coupled thereto for mixing the clock or synchronization signal with the deviation signal of for. This way produce a composite signal to be transferred in a single contact.