[go: up one dir, main page]

MX9702265A - Metodo y aparato para procesar informacion de tipo memoria dentro de un microprocesador. - Google Patents

Metodo y aparato para procesar informacion de tipo memoria dentro de un microprocesador.

Info

Publication number
MX9702265A
MX9702265A MX9702265A MX9702265A MX9702265A MX 9702265 A MX9702265 A MX 9702265A MX 9702265 A MX9702265 A MX 9702265A MX 9702265 A MX9702265 A MX 9702265A MX 9702265 A MX9702265 A MX 9702265A
Authority
MX
Mexico
Prior art keywords
memory
processing
microprocessor
type
instruction
Prior art date
Application number
MX9702265A
Other languages
English (en)
Other versions
MXPA97002265A (es
Inventor
Andrew F Glew
Glenn J Hinton
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of MXPA97002265A publication Critical patent/MXPA97002265A/es
Publication of MX9702265A publication Critical patent/MX9702265A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Un valor de tipo de memoria que identifica el tipo de memoria contenida con un gama de ubicaciones de memoria, se almacena explícitamente dentro de un microprocesador (200-216). Antes de procesar una microinstruccion de memoria tal como una carga o un almacenamiento, el tipo de memoria se determina (214-216) para la ubicacion de memoria identifica por la microinstruccion de memoria. Una vez que el tipo de memoria se conoce, se procesa la micro-instruccion de memoria (218-230) de acuerdo con cualquiera de una cantidad de protocolos de procesamiento incluyendo procesamiento de escritura directa (220), procesamiento de escritura hacia atrás (222), procesamiento con proteccion de escritura (224), procesamiento con restringida capacidad de guardar en bancos de memoria de alta velocidad (226), procesamiento en combinacion de escritura especulable no susceptible a guardar en bancos de memoria de alta velocidad (230) o procesamiento no susceptible a guardar en bancos de memoria de alta velocidad (228).. Al proporcionar informacion explícitamente de tipo de memoria dentro del microprocesador, el protocolo por el cual se procesa la microinstruccion puede ajustarse eficientemente a la medida al tipo de memoria. En una modalidad ejemplar el microprocesador es un microprocesador fuera-de-orden (200), capaz de generar microinstrucciones de memoria especulativa (202-204).
MX9702265A 1994-09-30 1995-08-24 Metodo y aparato para procesar informacion de tipo memoria dentro de un microprocesador. MX9702265A (es)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US31655094A 1994-09-30 1994-09-30
US316550 1994-09-30
PCT/US1995/010788 WO1996010789A1 (en) 1994-09-30 1995-08-24 Method and apparatus for processing memory-type information within a microprocessor

Publications (2)

Publication Number Publication Date
MXPA97002265A MXPA97002265A (es) 1997-06-01
MX9702265A true MX9702265A (es) 1997-06-28

Family

ID=23229519

Family Applications (1)

Application Number Title Priority Date Filing Date
MX9702265A MX9702265A (es) 1994-09-30 1995-08-24 Metodo y aparato para procesar informacion de tipo memoria dentro de un microprocesador.

Country Status (7)

Country Link
US (1) US5751996A (es)
EP (1) EP0783735B1 (es)
KR (1) KR100264401B1 (es)
AU (1) AU3494995A (es)
MX (1) MX9702265A (es)
WO (1) WO1996010789A1 (es)
ZA (1) ZA954460B (es)

Families Citing this family (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5819079A (en) * 1995-09-11 1998-10-06 Intel Corporation Instruction fetch on demand for uncacheable memory which avoids memory mapped I/O side effects in a processor with speculative instruction fetch
US5752265A (en) * 1996-06-13 1998-05-12 Compaq Computer Corporation Memory accessing in a multi-processor system using snooping
US5915262A (en) * 1996-07-22 1999-06-22 Advanced Micro Devices, Inc. Cache system and method using tagged cache lines for matching cache strategy to I/O application
US6189074B1 (en) 1997-03-19 2001-02-13 Advanced Micro Devices, Inc. Mechanism for storing system level attributes in a translation lookaside buffer
US5958045A (en) * 1997-04-02 1999-09-28 Advanced Micro Devices, Inc. Start of access instruction configured to indicate an access mode for fetching memory operands in a microprocessor
US5895484A (en) * 1997-04-14 1999-04-20 International Business Machines Corporation Method and system for speculatively accessing cache memory data within a multiprocessor data-processing system using a cache controller
US5924118A (en) * 1997-04-14 1999-07-13 International Business Machines Corporation Method and system for speculatively sourcing cache memory data prior to upstream cache invalidation within a multiprocessor data-processing system
US6351797B1 (en) * 1997-12-17 2002-02-26 Via-Cyrix, Inc. Translation look-aside buffer for storing region configuration bits and method of operation
US6301647B1 (en) * 1997-12-17 2001-10-09 Via-Cyrix, Inc. Real mode translation look-aside buffer and method of operation
US6185661B1 (en) * 1998-01-02 2001-02-06 Emc Corporation Worm magnetic storage device
US6038617A (en) * 1998-02-23 2000-03-14 National Instruments Corporation Auto configuration of a serial ROM by sensing an output of the serial ROM after transmission of a read instruction and an x-bit address to it's input
US6643745B1 (en) * 1998-03-31 2003-11-04 Intel Corporation Method and apparatus for prefetching data into cache
US6356270B2 (en) * 1998-03-31 2002-03-12 Intel Corporation Efficient utilization of write-combining buffers
US6073210A (en) * 1998-03-31 2000-06-06 Intel Corporation Synchronization of weakly ordered write combining operations using a fencing mechanism
US6433787B1 (en) 1998-11-23 2002-08-13 Nicholas J. N. Murphy Dynamic write-order organizer
JP4235299B2 (ja) * 1998-12-22 2009-03-11 キヤノン株式会社 カラー画像形成装置の製造方法
US6389527B1 (en) * 1999-02-08 2002-05-14 Kabushiki Kaisha Toshiba Microprocessor allowing simultaneous instruction execution and DMA transfer
US6269427B1 (en) 1999-03-18 2001-07-31 International Business Machines Corporation Multiple load miss handling in a cache memory system
US6321303B1 (en) 1999-03-18 2001-11-20 International Business Machines Corporation Dynamically modifying queued transactions in a cache memory system
US6311254B1 (en) 1999-03-18 2001-10-30 International Business Machines Corporation Multiple store miss handling in a cache memory memory system
US6366984B1 (en) * 1999-05-11 2002-04-02 Intel Corporation Write combining buffer that supports snoop request
US6446189B1 (en) 1999-06-01 2002-09-03 Advanced Micro Devices, Inc. Computer system including a novel address translation mechanism
DE19946716A1 (de) * 1999-09-29 2001-04-12 Infineon Technologies Ag Verfahren zum Betrieb eines Prozessorbusses
US6678810B1 (en) 1999-12-30 2004-01-13 Intel Corporation MFENCE and LFENCE micro-architectural implementation method and system
US6438673B1 (en) * 1999-12-30 2002-08-20 Intel Corporation Correlated address prediction
US6631452B1 (en) * 2000-04-28 2003-10-07 Idea Corporation Register stack engine having speculative load/store modes
US6510508B1 (en) 2000-06-15 2003-01-21 Advanced Micro Devices, Inc. Translation lookaside buffer flush filter
US6636939B1 (en) * 2000-06-29 2003-10-21 Intel Corporation Method and apparatus for processor bypass path to system memory
US6564305B1 (en) * 2000-09-20 2003-05-13 Hewlett-Packard Development Company Lp Compressing memory management in a device
US7287147B1 (en) 2000-12-29 2007-10-23 Mips Technologies, Inc. Configurable co-processor interface
US7237090B1 (en) 2000-12-29 2007-06-26 Mips Technologies, Inc. Configurable out-of-order data transfer in a coprocessor interface
US7168066B1 (en) * 2001-04-30 2007-01-23 Mips Technologies, Inc. Tracing out-of order load data
US7062761B2 (en) 2001-07-10 2006-06-13 Micron Technology, Inc. Dynamic arrays and overlays with bounds policies
US7127559B2 (en) 2001-07-10 2006-10-24 Micron Technology, Inc. Caching of dynamic arrays
US6665788B1 (en) 2001-07-13 2003-12-16 Advanced Micro Devices, Inc. Reducing latency for a relocation cache lookup and address mapping in a distributed memory system
US6681311B2 (en) * 2001-07-18 2004-01-20 Ip-First, Llc Translation lookaside buffer that caches memory type information
US7529912B2 (en) * 2002-02-12 2009-05-05 Via Technologies, Inc. Apparatus and method for instruction-level specification of floating point format
US7181596B2 (en) * 2002-02-12 2007-02-20 Ip-First, Llc Apparatus and method for extending a microprocessor instruction set
US7315921B2 (en) * 2002-02-19 2008-01-01 Ip-First, Llc Apparatus and method for selective memory attribute control
US7328328B2 (en) * 2002-02-19 2008-02-05 Ip-First, Llc Non-temporal memory reference control mechanism
US7395412B2 (en) * 2002-03-08 2008-07-01 Ip-First, Llc Apparatus and method for extending data modes in a microprocessor
US7546446B2 (en) * 2002-03-08 2009-06-09 Ip-First, Llc Selective interrupt suppression
US7302551B2 (en) * 2002-04-02 2007-11-27 Ip-First, Llc Suppression of store checking
US7380103B2 (en) 2002-04-02 2008-05-27 Ip-First, Llc Apparatus and method for selective control of results write back
US7155598B2 (en) * 2002-04-02 2006-12-26 Ip-First, Llc Apparatus and method for conditional instruction execution
US7185180B2 (en) * 2002-04-02 2007-02-27 Ip-First, Llc Apparatus and method for selective control of condition code write back
US7373483B2 (en) 2002-04-02 2008-05-13 Ip-First, Llc Mechanism for extending the number of registers in a microprocessor
US7380109B2 (en) * 2002-04-15 2008-05-27 Ip-First, Llc Apparatus and method for providing extended address modes in an existing instruction set for a microprocessor
US6922745B2 (en) * 2002-05-02 2005-07-26 Intel Corporation Method and apparatus for handling locks
GB2396930B (en) * 2002-11-18 2005-09-07 Advanced Risc Mach Ltd Apparatus and method for managing access to a memory
US7290093B2 (en) * 2003-01-07 2007-10-30 Intel Corporation Cache memory to support a processor's power mode of operation
US7159076B2 (en) * 2003-06-24 2007-01-02 Research In Motion Limited Cache operation with non-cache memory
US20050114559A1 (en) * 2003-11-20 2005-05-26 Miller George B. Method for efficiently processing DMA transactions
JP2005190161A (ja) * 2003-12-25 2005-07-14 Matsushita Electric Ind Co Ltd データ処理装置およびコンパイラ装置
JP4576323B2 (ja) * 2004-12-10 2010-11-04 富士通株式会社 データ転送装置およびデータ転送方法
US20060242390A1 (en) * 2005-04-26 2006-10-26 Intel Corporation Advanced load address table buffer
US8275976B2 (en) * 2005-08-29 2012-09-25 The Invention Science Fund I, Llc Hierarchical instruction scheduler facilitating instruction replay
US8296550B2 (en) * 2005-08-29 2012-10-23 The Invention Science Fund I, Llc Hierarchical register file with operand capture ports
US20070083735A1 (en) * 2005-08-29 2007-04-12 Glew Andrew F Hierarchical processor
US7644258B2 (en) * 2005-08-29 2010-01-05 Searete, Llc Hybrid branch predictor using component predictors each having confidence and override signals
US9176741B2 (en) * 2005-08-29 2015-11-03 Invention Science Fund I, Llc Method and apparatus for segmented sequential storage
US7949834B2 (en) * 2007-01-24 2011-05-24 Qualcomm Incorporated Method and apparatus for setting cache policies in a processor
US8055805B2 (en) * 2009-03-31 2011-11-08 Intel Corporation Opportunistic improvement of MMIO request handling based on target reporting of space requirements
US9367356B2 (en) * 2010-06-17 2016-06-14 Microsoft Technology Licensing, Llc Resource access control
JP2012198803A (ja) * 2011-03-22 2012-10-18 Fujitsu Ltd 演算処理装置及び演算処理方法
US8910136B2 (en) * 2011-09-02 2014-12-09 International Business Machines Corporation Generating code that calls functions based on types of memory
US20140317337A1 (en) * 2011-12-30 2014-10-23 Leena K. Puthiyedath Metadata management and support for phase change memory with switch (pcms)
JP6127907B2 (ja) * 2012-11-12 2017-05-17 富士通株式会社 演算処理装置及び演算処理装置の制御方法
US9471511B2 (en) * 2013-11-24 2016-10-18 Truly Protect Oy System and methods for CPU copy protection of a computing device
US9756048B2 (en) 2013-11-24 2017-09-05 Truly Protect Oy System and methods for executing encrypted managed programs
US9658963B2 (en) * 2014-12-23 2017-05-23 Intel Corporation Speculative reads in buffered memory
JP6729168B2 (ja) 2016-08-22 2020-07-22 ブラザー工業株式会社 コンテンツ処理装置
US11853231B2 (en) 2021-06-24 2023-12-26 Ati Technologies Ulc Transmission of address translation type packets
US20230153094A1 (en) * 2021-11-18 2023-05-18 Toyota Motor North America, Inc. Robust over the air reprogramming
US11860670B2 (en) 2021-12-16 2024-01-02 Intel Corporation Accessing a memory using index offset information
US12287740B2 (en) * 2023-06-07 2025-04-29 Dell Products L.P Data caching strategies for storage with ownership of logical address slices

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091846A (en) * 1986-10-03 1992-02-25 Intergraph Corporation Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
US5185878A (en) * 1988-01-20 1993-02-09 Advanced Micro Device, Inc. Programmable cache memory as well as system incorporating same and method of operating programmable cache memory
US5297270A (en) * 1989-11-13 1994-03-22 Zenith Data Systems Corporation Programmable cache memory which associates each section of main memory to be cached with a status bit which enables/disables the caching accessibility of the particular section, and with the capability of functioning with memory areas of varying size
US5353431A (en) * 1991-04-29 1994-10-04 Intel Corporation Memory address decoder with storage for memory attribute information
US5325504A (en) * 1991-08-30 1994-06-28 Compaq Computer Corporation Method and apparatus for incorporating cache line replacement and cache write policy information into tag directories in a cache system
US5386547A (en) * 1992-01-21 1995-01-31 Digital Equipment Corporation System and method for exclusive two-level caching

Also Published As

Publication number Publication date
US5751996A (en) 1998-05-12
EP0783735A1 (en) 1997-07-16
KR100264401B1 (ko) 2000-08-16
WO1996010789A1 (en) 1996-04-11
EP0783735B1 (en) 2011-08-24
EP0783735A4 (en) 2004-10-20
ZA954460B (en) 1996-02-05
KR970706538A (ko) 1997-11-03
AU3494995A (en) 1996-04-26

Similar Documents

Publication Publication Date Title
MX9702265A (es) Metodo y aparato para procesar informacion de tipo memoria dentro de un microprocesador.
HK1049529B (zh) 在一個多線程處理器內不同線程之間劃分一個資源的方法及裝置
EP0918288A3 (en) Apparatus for spatial and temporal sampling in a computer memory system
DK0938703T3 (da) Accelerator for tidstro programsprog
SE9804169L (sv) Förfarande och anordning avseende en elektronisk börs
AU2003214934A8 (en) Method and system for multimedia tags
EP0851344A3 (en) Combined branch prediction and cache prefetch in a microprocessor
EP1182571A3 (en) TLB operations based on shared bit
BR9612772A (pt) Método e aparelho de software contra falsificação digital
GB2354863A (en) Methods and apparatus for updating a nonvolatile memory
WO2002054230A3 (en) System and method for prefetching data into a cache based on miss distance
WO2006118667A3 (en) Prefetching across a page boundary
EP0938044A3 (en) Methods and apparatus for reducing interference in a branch history table of a microprocessor
EP0936543A3 (en) Program transformation method and program transformation system
EP0750258A3 (en) Memory state recovering apparatus
EP1439460A3 (en) Apparatus and method for invalidation of redundant entries in a branch target address cache
EP0772123A3 (en) Data processing system with instruction prefetch
WO2004102376A3 (en) Apparatus and method to provide multithreaded computer processing
DE69521047D1 (de) Behälter zum zerreissen von zylinderförmigen gegenständen mit einem weiteren behandlungsbehälter
WO2005013039A3 (en) Prefetch control in a data processing system
EP0285346A3 (en) Cache memory device
EP1109095A3 (en) Instruction prefetch and branch prediction circuit
EP0374370A3 (en) Method for storing into non-exclusive cache lines in multiprocessor systems
ATE220810T1 (de) Informationsverarbeitungssystem mit einem cachespeicher und vorrichtung zur datenvorausholung
WO2001057656A3 (en) Reduced size object headers