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MX2019009532A - Dispositivo semiconductor y metodo de fabricacion del mismo. - Google Patents

Dispositivo semiconductor y metodo de fabricacion del mismo.

Info

Publication number
MX2019009532A
MX2019009532A MX2019009532A MX2019009532A MX2019009532A MX 2019009532 A MX2019009532 A MX 2019009532A MX 2019009532 A MX2019009532 A MX 2019009532A MX 2019009532 A MX2019009532 A MX 2019009532A MX 2019009532 A MX2019009532 A MX 2019009532A
Authority
MX
Mexico
Prior art keywords
region
type
conductivity
drift region
substrate
Prior art date
Application number
MX2019009532A
Other languages
English (en)
Other versions
MX384166B (es
Inventor
Hayashi Tetsuya
Ni Wei
Hayami Yasuaki
Tanaka Ryota
Takemoto Keisuke
Original Assignee
Nissan Motor
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissan Motor filed Critical Nissan Motor
Publication of MX2019009532A publication Critical patent/MX2019009532A/es
Publication of MX384166B publication Critical patent/MX384166B/es

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/158—Dispositions
    • H10P30/22—
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
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    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
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    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
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    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H10D30/0287—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs using recessing of the source electrodes
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    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H10D30/0289—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
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    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
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    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/663—Vertical DMOS [VDMOS] FETs having both source contacts and drain contacts on the same surface, i.e. up-drain VDMOS
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
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    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
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    • H10D62/149—Source or drain regions of field-effect devices
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    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
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    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0156—Manufacturing their doped wells
    • H10P30/2042—
    • H10P30/222—

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Se incluyen una primera región (4) de deriva del primer tipo de conductividad formada en una primera superficie principal de un sustrato (1), y una segunda región (41) de deriva del primer tipo de conductividad formada en la primera superficie principal del sustrato (1), la segunda región de deriva formada para llegar a una posición más profunda del sustrato (1) que una posición de la primera región (4) de deriva. Se incluyen adicionalmente una región de pozo del segundo tipo de conductividad en contacto con la segunda región de deriva, una región de fuente del primer tipo de conductividad formada para extenderse en una dirección perpendicular a una superficie de la región de pozo, y una región de drenaje del primer tipo de conductividad separada de la región de pozo, la región de drenaje formada para extenderse en una dirección perpendicular a una superficie de la primera región de deriva. Debido a que una trayectoria de flujo de los electrones después de pasar a través de un canal puede ser ensanchada, una resistencia puede ser reducida.
MX2019009532A 2017-02-14 2017-02-14 Dispositivo semiconductor y método de fabricación del mismo. MX384166B (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2017/005333 WO2018150467A1 (ja) 2017-02-14 2017-02-14 半導体装置および半導体装置の製造方法

Publications (2)

Publication Number Publication Date
MX2019009532A true MX2019009532A (es) 2019-09-16
MX384166B MX384166B (es) 2025-03-14

Family

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Family Applications (1)

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MX2019009532A MX384166B (es) 2017-02-14 2017-02-14 Dispositivo semiconductor y método de fabricación del mismo.

Country Status (11)

Country Link
US (1) US20200020775A1 (es)
EP (1) EP3584824A4 (es)
JP (1) JP6725055B2 (es)
KR (1) KR102056037B1 (es)
CN (1) CN110291620B (es)
BR (1) BR112019016822A2 (es)
CA (1) CA3053635C (es)
MX (1) MX384166B (es)
MY (1) MY186880A (es)
RU (1) RU2719569C1 (es)
WO (1) WO2018150467A1 (es)

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CN113394291A (zh) * 2021-04-29 2021-09-14 电子科技大学 横向功率半导体器件
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JP2023105484A (ja) * 2022-01-19 2023-07-31 日産自動車株式会社 半導体装置及びその製造方法
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CA3053635C (en) 2020-08-18
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