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MX2015008949A - Dispositivo semiconductor que tiene caracteristicas para evitar la ingenieria inversa. - Google Patents

Dispositivo semiconductor que tiene caracteristicas para evitar la ingenieria inversa.

Info

Publication number
MX2015008949A
MX2015008949A MX2015008949A MX2015008949A MX2015008949A MX 2015008949 A MX2015008949 A MX 2015008949A MX 2015008949 A MX2015008949 A MX 2015008949A MX 2015008949 A MX2015008949 A MX 2015008949A MX 2015008949 A MX2015008949 A MX 2015008949A
Authority
MX
Mexico
Prior art keywords
transistor
channel
features
semiconductor device
reverse engineering
Prior art date
Application number
MX2015008949A
Other languages
English (en)
Other versions
MX344039B (es
Inventor
Robert Francis Tenczar
Michael Clinton Hoke
William Eli Thacker
Original Assignee
Secure Silicon Layer Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Secure Silicon Layer Inc filed Critical Secure Silicon Layer Inc
Publication of MX2015008949A publication Critical patent/MX2015008949A/es
Publication of MX344039B publication Critical patent/MX344039B/es

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/86—Secure or tamper-resistant housings
    • G06F21/87—Secure or tamper-resistant housings by means of encapsulation, e.g. for integrated circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/38—Doping programmed, e.g. mask ROM
    • H10W42/40—
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Mathematical Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Read Only Memory (AREA)

Abstract

Un circuito ROM incluye un primer transistor de N canal que tiene una salida y que tiene geometría de dispositivo y características de dispositivo adaptadas para polarizar la salida a un nivel predeterminado cuando un circuito de P canal es conectado al primer transistor de N canal, un transistor de paso conectado entre la salida y un bus de datos, el transistor de paso conectado a una línea de palabras, la línea de palabras adaptada para ENCENDER el transistor de paso cuando se asevera la línea de palabras; y el circuito de P canal conectado al bus de datos y adaptado para proporcionar corriente de fuga para cargar una compuerta en el primer transistor de N canal cuando el transistor de paso es ENCENDIDO.
MX2015008949A 2013-01-11 2014-01-07 Dispositivo semiconductor que tiene caracteristicas para evitar la ingenieria inversa. MX344039B (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/739,463 US9218511B2 (en) 2011-06-07 2013-01-11 Semiconductor device having features to prevent reverse engineering
PCT/US2014/010437 WO2014110010A1 (en) 2013-01-11 2014-01-07 Semiconductor device having features to prevent reverse engineering

Publications (2)

Publication Number Publication Date
MX2015008949A true MX2015008949A (es) 2015-09-29
MX344039B MX344039B (es) 2016-12-01

Family

ID=51164998

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2015008949A MX344039B (es) 2013-01-11 2014-01-07 Dispositivo semiconductor que tiene caracteristicas para evitar la ingenieria inversa.

Country Status (9)

Country Link
US (2) US9218511B2 (es)
EP (1) EP2943981B1 (es)
CN (1) CN104969349B (es)
AP (1) AP2015008586A0 (es)
BR (1) BR112015016671A2 (es)
CA (1) CA2897486A1 (es)
EA (1) EA201591225A1 (es)
MX (1) MX344039B (es)
WO (1) WO2014110010A1 (es)

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US8975748B1 (en) * 2011-06-07 2015-03-10 Secure Silicon Layer, Inc. Semiconductor device having features to prevent reverse engineering
US9762245B1 (en) * 2016-06-14 2017-09-12 Globalfoundries Inc. Semiconductor structure with back-gate switching
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Also Published As

Publication number Publication date
US9972398B2 (en) 2018-05-15
EP2943981A4 (en) 2016-08-17
CA2897486A1 (en) 2014-07-17
AP2015008586A0 (en) 2015-07-31
US9218511B2 (en) 2015-12-22
EP2943981A1 (en) 2015-11-18
WO2014110010A1 (en) 2014-07-17
CN104969349A (zh) 2015-10-07
MX344039B (es) 2016-12-01
US20140198554A1 (en) 2014-07-17
CN104969349B (zh) 2018-03-02
EP2943981B1 (en) 2017-09-06
EA201591225A1 (ru) 2016-02-29
US20160005485A1 (en) 2016-01-07
BR112015016671A2 (pt) 2017-07-11

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Owner name: DEPUY SYNTHES PRODUCTS, INC.

FG Grant or registration