[go: up one dir, main page]

MX2013015121A - Transferencia de datos simultanea y control de error para reducir la latencia y mejorar la capacidad de procesamiento a un anfitrion. - Google Patents

Transferencia de datos simultanea y control de error para reducir la latencia y mejorar la capacidad de procesamiento a un anfitrion.

Info

Publication number
MX2013015121A
MX2013015121A MX2013015121A MX2013015121A MX2013015121A MX 2013015121 A MX2013015121 A MX 2013015121A MX 2013015121 A MX2013015121 A MX 2013015121A MX 2013015121 A MX2013015121 A MX 2013015121A MX 2013015121 A MX2013015121 A MX 2013015121A
Authority
MX
Mexico
Prior art keywords
host
block
error
data transfer
error control
Prior art date
Application number
MX2013015121A
Other languages
English (en)
Inventor
Christopher J Sarcone
David G Conroy
Jim Keller
Original Assignee
Apple Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Apple Inc filed Critical Apple Inc
Publication of MX2013015121A publication Critical patent/MX2013015121A/es

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/08—Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

Las modalidades descritas proporcionan un sistema que transfiere datos desde un dispositivo de almacenamiento a un anfitrión. El sistema incluye un mecanismo de comunicación que recibe una solicitud para leer un conjunto de bloques desde el anfitrión. Después, tras leer cada bloque del conjunto de bloques desde el dispositivo de almacenamiento, el mecanismo de comunicación transfiere el bloque a través de una interfaz con el anfitrión. El sistema también incluye un aparato de detección de error que realiza la detección de error en el bloque tras leer el bloque y un aparato de corrección de error que realiza corrección de error en el bloque si se detecta un error en el bloque. El mecanismo de comunicación puede entonces retransferir el bloque al anfitrión después de que el error es eliminado del bloque.
MX2013015121A 2011-09-02 2012-08-28 Transferencia de datos simultanea y control de error para reducir la latencia y mejorar la capacidad de procesamiento a un anfitrion. MX2013015121A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/224,714 US8656251B2 (en) 2011-09-02 2011-09-02 Simultaneous data transfer and error control to reduce latency and improve throughput to a host
PCT/US2012/052713 WO2013033121A1 (en) 2011-09-02 2012-08-28 Simultaneous data transfer and error control to reduce latency and improve throughput to a host

Publications (1)

Publication Number Publication Date
MX2013015121A true MX2013015121A (es) 2014-03-31

Family

ID=46801657

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2013015121A MX2013015121A (es) 2011-09-02 2012-08-28 Transferencia de datos simultanea y control de error para reducir la latencia y mejorar la capacidad de procesamiento a un anfitrion.

Country Status (9)

Country Link
US (2) US8656251B2 (es)
EP (1) EP2751688A1 (es)
JP (1) JP2014529132A (es)
KR (1) KR101598726B1 (es)
CN (1) CN103748561B (es)
AU (1) AU2012302094B2 (es)
BR (1) BR112014002172A2 (es)
MX (1) MX2013015121A (es)
WO (1) WO2013033121A1 (es)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8988800B1 (en) * 2009-09-15 2015-03-24 Marvell International Ltd. Error correction for storage devices
JP5542787B2 (ja) * 2011-12-08 2014-07-09 シャープ株式会社 画像形成装置
MY180992A (en) 2013-03-13 2020-12-15 Intel Corp Memory latency management
US9323610B2 (en) * 2014-01-30 2016-04-26 Sandisk Technologies Inc. Non-blocking commands
US9851901B2 (en) 2014-09-26 2017-12-26 Western Digital Technologies, Inc. Transfer of object memory references in a data storage device
KR102229024B1 (ko) 2014-12-03 2021-03-17 삼성전자주식회사 스스로 에러를 검출하고 로그를 저장할 수 있는 데이터 저장 장치와 이를 포함하는 시스템
DE102015209033A1 (de) * 2015-05-18 2016-11-24 Robert Bosch Gmbh Verfahren und Vorrichtung zum Liefern einer Prüfantwort
US11588783B2 (en) * 2015-06-10 2023-02-21 Cisco Technology, Inc. Techniques for implementing IPV6-based distributed storage space
US20170141878A1 (en) * 2015-11-16 2017-05-18 Western Digital Technologies, Inc. Systems and methods for sending data from non-volatile solid state devices before error correction
US10768856B1 (en) * 2018-03-12 2020-09-08 Amazon Technologies, Inc. Memory access for multiple circuit components
CN114978441B (zh) * 2022-06-14 2024-07-12 四川禹明光电技术有限公司 一种用于光纤传感同步传输的监测校正系统

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57211177A (en) * 1981-06-23 1982-12-24 Hitachi Metals Ltd Picture reproducing device
JPS5819712A (ja) * 1981-07-29 1983-02-04 Hitachi Ltd デ−タ記録方式
US5379417A (en) * 1991-11-25 1995-01-03 Tandem Computers Incorporated System and method for ensuring write data integrity in a redundant array data storage system
US5490148A (en) * 1993-12-15 1996-02-06 Motorola, Inc. Bit error rate estimator
US5694262A (en) * 1994-01-31 1997-12-02 Fujitsu Ltd. Method and apparatus for transferring data and making on-the-fly correction of errors
US5488702A (en) * 1994-04-26 1996-01-30 Unisys Corporation Data block check sequence generation and validation in a file cache system
JP4105819B2 (ja) * 1999-04-26 2008-06-25 株式会社ルネサステクノロジ 記憶装置およびメモリカード
JP4437519B2 (ja) * 2001-08-23 2010-03-24 スパンション エルエルシー 多値セルメモリ用のメモリコントローラ
JP4140344B2 (ja) * 2002-10-30 2008-08-27 日本ビクター株式会社 復号化装置及びコンピュータプログラム
JP2005141341A (ja) * 2003-11-05 2005-06-02 Hitachi Ltd メモリ制御装置、および、メモリ制御方法
US7624298B2 (en) * 2004-02-03 2009-11-24 Panasonic Corporation Memory card, data processor, memory card control method and memory card setting
US7426672B2 (en) * 2005-04-28 2008-09-16 International Business Machines Corporation Method for implementing processor bus speculative data completion
US7793059B2 (en) * 2006-01-18 2010-09-07 Apple Inc. Interleaving policies for flash memory
CN101689131B (zh) * 2006-12-06 2013-03-20 弗森-艾奥公司 用于共享的、前端、分布式raid的装置、系统和方法
JP4609522B2 (ja) * 2008-04-24 2011-01-12 パナソニック株式会社 記憶装置
JP2010039779A (ja) * 2008-08-05 2010-02-18 Sony Corp リーダライタ、情報読み出し方法、通信システムおよび通信方法
US8438453B2 (en) * 2009-05-06 2013-05-07 Apple Inc. Low latency read operation for managed non-volatile memory
US20110041005A1 (en) * 2009-08-11 2011-02-17 Selinger Robert D Controller and Method for Providing Read Status and Spare Block Management Information in a Flash Memory System
US8639870B2 (en) * 2011-01-14 2014-01-28 Oracle International Corporation String searching within peripheral storage devices

Also Published As

Publication number Publication date
CN103748561A (zh) 2014-04-23
CN103748561B (zh) 2019-01-08
US20130061111A1 (en) 2013-03-07
KR20140025595A (ko) 2014-03-04
BR112014002172A2 (pt) 2017-03-01
EP2751688A1 (en) 2014-07-09
AU2012302094A1 (en) 2014-01-16
AU2012302094B2 (en) 2016-02-18
KR101598726B1 (ko) 2016-02-29
JP2014529132A (ja) 2014-10-30
WO2013033121A1 (en) 2013-03-07
US8656251B2 (en) 2014-02-18
US9015557B2 (en) 2015-04-21
US20140195872A1 (en) 2014-07-10

Similar Documents

Publication Publication Date Title
MX2013015121A (es) Transferencia de datos simultanea y control de error para reducir la latencia y mejorar la capacidad de procesamiento a un anfitrion.
MX2010008883A (es) Transferencia bidireccional de datos dentro de una operacion i/o individual.
MX364783B (es) Estructuras de unidades de estado sólido.
WO2012100087A3 (en) Apparatus, system, and method for managing out-of-service conditions
EP2248028A4 (en) SEMICONDUCTOR STORAGE DEVICE, METHOD FOR CONTROLLING THE DEVICE, AND ERROR CORRECTION SYSTEM
WO2012177681A3 (en) Systems and methods for digital forensic triage
MY154086A (en) Data processing apparatus and method
GB2506833A (en) Method and apparatus for using cache memory in a system that supports a low power state
WO2010110955A3 (en) System and method of managing memory at a portable computing device and a portable computing device docking station
WO2011159805A3 (en) Apparatus, system, and method for providing error correction
GB2485696A (en) Data storage
WO2012166725A3 (en) Apparatus and methods for providing data integrity
WO2012166726A3 (en) Apparatus and methods for providing data integrity
JP2012108677A5 (es)
BR112013023013A2 (pt) método e sistema para testar o conteúdo de usuário de um dispositivo de comunicação móvel determinado e meio de leitura de computador não transitório.
MX2012003331A (es) Datos de entretenimiento de cara compartidos.
WO2013080027A3 (en) Interrupt handling systems and methods for pcie bridges with multiple buses
GB201102541D0 (en) Storage device,data processing device,registration method,and recording medium
EP2565772A4 (en) STORAGE ASSEMBLY, STORAGE SYSTEM, AND METHOD OF ACCESSING DATA
GB2509849A (en) Method and apparatus for injecting errors into memory
GB201307478D0 (en) Systems and methods for data access protection
EP3188002A4 (en) Method and apparatus for reading and writing data, storage device and computer system
EP2631833A4 (en) METHOD, DEVICE AND SYSTEM FOR VERIFYING THE CONNECTION OF A DATA CARD AND MOBILE HOST THEREFOR
WO2012177057A3 (en) Semiconductor storage device-based high-speed cache storage system
TW200641624A (en) Technical fieldmethods and apparatus for list transfers using dma transfers in a multi-processor system

Legal Events

Date Code Title Description
HH Correction or change in general
FG Grant or registration