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MX2009007948A - Metodo y aparato para fijar politicas para la memoria cache en un procesador. - Google Patents

Metodo y aparato para fijar politicas para la memoria cache en un procesador.

Info

Publication number
MX2009007948A
MX2009007948A MX2009007948A MX2009007948A MX2009007948A MX 2009007948 A MX2009007948 A MX 2009007948A MX 2009007948 A MX2009007948 A MX 2009007948A MX 2009007948 A MX2009007948 A MX 2009007948A MX 2009007948 A MX2009007948 A MX 2009007948A
Authority
MX
Mexico
Prior art keywords
processor
cache
policies
management unit
memory management
Prior art date
Application number
MX2009007948A
Other languages
English (en)
Inventor
Michael William Morrow
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of MX2009007948A publication Critical patent/MX2009007948A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

De conformidad con los métodos y el aparato descritos en la presente, las políticas de almacenamiento en la memoria caché del procesador se determinan utilizando la información de la política para la memoria caché asociada a un dispositivo de memoria de destino al que se accedió durante una operación en la memoria. De conformidad con una modalidad de un procesador, el procesador contiene al menos una memoria caché y una unidad de gestión de la memoria. Esta al menos una memoria caché está configurada para que almacene información local para el procesador. La unidad de gestión de la memoria está configurada para fijar una o más políticas para la memoria caché en la al menos una memoria caché. La unidad de gestión de la memoria fija la o las políticas de la memoria caché con base en la información de la política para la memoria caché asociada al o a los dispositivos de memoria de destino configurados para almacenar la información utilizada por el procesador.
MX2009007948A 2007-01-24 2008-01-24 Metodo y aparato para fijar politicas para la memoria cache en un procesador. MX2009007948A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/626,434 US7949834B2 (en) 2007-01-24 2007-01-24 Method and apparatus for setting cache policies in a processor
PCT/US2008/051953 WO2008092032A1 (en) 2007-01-24 2008-01-24 Method and apparatus for setting cache policies in a processor

Publications (1)

Publication Number Publication Date
MX2009007948A true MX2009007948A (es) 2009-08-07

Family

ID=39456426

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2009007948A MX2009007948A (es) 2007-01-24 2008-01-24 Metodo y aparato para fijar politicas para la memoria cache en un procesador.

Country Status (11)

Country Link
US (1) US7949834B2 (es)
EP (1) EP2115599B1 (es)
JP (1) JP5313168B2 (es)
KR (1) KR101079970B1 (es)
CN (1) CN101589374B (es)
BR (1) BRPI0806756A2 (es)
CA (1) CA2674868C (es)
MX (1) MX2009007948A (es)
RU (1) RU2427892C2 (es)
TW (1) TWI446166B (es)
WO (1) WO2008092032A1 (es)

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US20130042238A1 (en) * 2011-08-12 2013-02-14 International Business Machines Corporation Optimized Virtual Function Translation Entry Memory Caching
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US10133488B2 (en) * 2014-03-17 2018-11-20 Primaryio, Inc. Apparatus and method for cache provisioning, configuration for optimal application performance
US10146437B2 (en) 2014-03-17 2018-12-04 Primaryio, Inc. Tier aware caching solution to increase application performance
US9715455B1 (en) * 2014-05-05 2017-07-25 Avago Technologies General Ip (Singapore) Pte. Ltd. Hint selection of a cache policy
CN107810491B (zh) * 2015-05-27 2022-02-01 谷歌有限责任公司 用于管理并控制存储器高速缓存的方法和系统
US20170255569A1 (en) * 2016-03-01 2017-09-07 Qualcomm Incorporated Write-allocation for a cache based on execute permissions
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Also Published As

Publication number Publication date
CA2674868A1 (en) 2008-07-31
RU2009131695A (ru) 2011-02-27
JP5313168B2 (ja) 2013-10-09
EP2115599A1 (en) 2009-11-11
WO2008092032A1 (en) 2008-07-31
EP2115599B1 (en) 2017-07-19
RU2427892C2 (ru) 2011-08-27
CA2674868C (en) 2015-02-03
CN101589374B (zh) 2012-07-04
BRPI0806756A2 (pt) 2011-09-13
CN101589374A (zh) 2009-11-25
TW200842572A (en) 2008-11-01
TWI446166B (zh) 2014-07-21
KR101079970B1 (ko) 2011-11-04
US20080177952A1 (en) 2008-07-24
JP2010517179A (ja) 2010-05-20
US7949834B2 (en) 2011-05-24
KR20090108716A (ko) 2009-10-16

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