DEVICE FOR CAPTURING MULTIPLE DATA PACKAGES IN A DATA SIGNAL FOR BACKGROUND ANALYSIS OF THE INVENTION 1. Field of the Invention The present invention relates to methods for capturing data packets within a digital data signal, and in particular to methods for capturing data packets within a digital data signal by capturing predetermined portions of the data signal to enable a simpler and more efficient data analysis. 2. Related techniques More and more popular and well-known data communication systems communicate through digital data signals in which the data is distributed among several data packets that are transmitted sequentially and then reassembled within the receiver, often with transmission along several paths of different signals (for example, as it is done on the Internet). A conventional test equipment to measure these data signals captures these data packets, stores them and then transfers them for analysis. Frequently, the transfer and analysis of the captured data requires a longer time lapse than the process through which they are captured within the data signal, in part due to the need to transfer the captured data to a data loop.
remote analysis (for example, a separate computer from the test equipment). Consecutive data packets are often narrowly spaced, particularly within data signals transmitted at high data rates. Accordingly, a conventional test equipment will often not measure consecutive packets but will capture non-adjacent packets spaced in time by a range that is approximately the time required for analysis or measurement. However, it is often desirable to capture consecutive packets, for example, to analyze power variations from one packet to another. To do this with conventional test equipment, it is generally necessary to increase the time interval available to capture the data packets, thereby causing the capture window to become equal to the duration of the number of consecutive data packets You want to capture and analyze. However, this is a disadvantage due to the fact that the increase of the capture window will also slow down the overall operation of data capture and analysis since more data must be transferred between the capture memory and the analysis engine. Furthermore, in many communication systems, the data packets are not closely spaced which means that a large part of the captured data is not used since it corresponds to the
spaces between consecutive data packets. Likewise, in multiple input, multiple output (MIMO) systems with a single data analysis engine, as is frequently done in a production test environment, the time efficiency in capturing and analyzing data packets becomes even more important. As is known, a MIMO system uses multiple transmitters operated in parallel. Testing one transmitter at a time requires that the overall system be maintained in a longer transmission operation state and therefore potentially affect its performance due to the increased heat buildup. To effectively avoid this problem, you must test a transmitter, turn off the unit, wait for its stabilization in the off state, then turn on the unit again to test the next transmitter, etc. As a result, the overall test time increases significantly. SUMMARY OF THE INVENTION In accordance with the present invention, there is provided a switching and control circuit for selectively combining several data signals in order to provide a composite signal corresponding to one or more of the plurality of data signals, and an activation signal to control the capture of selected portions of the composite signal.
In accordance with one embodiment of the present invention, the switching and control circuit for selectively combining a plurality of data signals for the purpose of providing a composite signal corresponding to one or more of the plurality of data signals and a signal of activation to control the capture of selected portions of the composite signal includes: a routing circuit and signal detection, a signal combining circuit and a control circuit. The routing and signal detection circuit responds to a plurality of data signals and a plurality of control signals with assertion and negation control signal states, respectively by transferring one or more of the plurality of data signals and providing one or more detection signals indicative of respective magnitudes of one or more of the plurality of data signals. The signal combining circuit is connected to the routing and signal detection circuit and responds to the transported signal or the various signals carried from the plurality of data signals by providing a corresponding composite signal. The control circuit is connected to the routing and signal detection circuit and responds to the signal or to the various detection signals by providing the plurality of control signals and an activation signal indicating the respective magnitudes
one or several of the plurality of data signals and the respective assertion and negation control signal state. In accordance with another embodiment of the present invention, the switching and control circuit for selectively combining a plurality of data signals to provide a composite signal corresponding to one or more of the plurality of data signals and an activation signal to control the capture of selected portions of the composite signal includes: a router means and signal detector, a signal combining means and a controller means. The router and signal detector means is for receiving a plurality of data signals and a plurality of control signals with respective assertion and negation control signal states, and in response to this transporting one or more of the plurality of signals. data signals and providing one or more detection signals indicative of derogatory magnitudes of one or more of the plurality of data signals. The signal combiner means is for combining the transported data signal or the various data signals transported from the plurality of data signals to provide a corresponding composite signal. The controller means is for receiving the detection signal or the various detection signals and in response to this generating the plurality of
control signals and an activation signal indicating the respective magnitudes of one or more of the plurality of data signals and the respective assertion and negation control signal states. In accordance with another embodiment of the present invention, the switching and control circuit for selectively combining a plurality of data signals to provide a composite signal corresponding to one or more of the plurality of data signals, and an activation signal for controlling the capture of selected portions of the composite signal includes: a signal routing circuit, a signal combination circuit, a signal detection circuit and a control circuit. The signal routing circuit responds to a plurality of data signals and a plurality of control signals with respective assertion and negation control signal states, by transporting one or more of the plurality of data signals. The signal combining circuit is connected to the signal routing circuit and responds to the transported data signal or the various data signals transported from the plurality of data signals by providing a corresponding composite signal. The signal detection circuit is connected to the signal combination circuit and responds to the composite signal by providing a signal of
Indicator detection of the magnitude of the composite signal. The control circuit is connected to the signal routing circuit and the signal detection circuit, and responds to the detection signal by providing the plurality of control signals and an activation signal indicative of the magnitude of the composite signal and the states of assertion and negation control signal respectively. In accordance with another embodiment of the present invention, a switching and control circuit for selectively combining a plurality of data signals to provide a composite signal corresponding to one or more of the plurality of data signals, and an activation signal for controlling the capture of selected portions of the composite signal includes: a signal router means, a signal combiner means, a signal detector means and a control circuit. The signal routing circuit responds to a plurality of data signals and a plurality of control signals with respective assertion and negation control signal states, by transporting one or more of the plurality of data signals. The signal combining circuit is connected to the signal routing circuit and responds to the transported data signal or the various data signals transported from the plurality of data signals by providing a composite signal
correspondent. The signal detection circuit is connected to the signal combining circuit and responds to the composite signal by providing a detection signal indicative of the magnitude of the composite signal. The control circuit is connected to the signal routing circuit and the signal detection circuit, and responds to the detection signal by providing the plurality of control signals and an activation signal indicative of the magnitude of the composite signal and the states of assertion and negation control signal respectively. In accordance with another embodiment of the present invention, a switching and control circuit for selectively combining a plurality of data signals to provide a composite signal corresponding to one or more of the plurality of data signals, and an activation signal for controlling the capture of selected portions of the composite signal includes: a signal router means, a signal combiner means, a signal detector means and a controller means. The signal router means is for receiving a plurality of data signals and a plurality of control signals with respective assertion and negation control signal states, and in response to this transporting one or more of the plurality of data signals. . The combined signal means is to combine the data signal transported or
the various data signals conveyed from the plurality of data signals to provide a corresponding composite signal. The signal detector means is for detecting the composite signal to provide a detection signal indicative of the magnitude of the composite signal. The controller means is for providing the plurality of control signals and on receiving the detection signal and in response to this providing an activation signal indicative of the magnitude of the composite signal and the assertion and negation control signal states respective. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a diagram illustrating a conventional method for each capture and analysis of data packets. Figure 2 is a diagram illustrating another conventional method for capturing and analyzing data packets. Figure 3A is a diagram illustrating a method for capturing data packets for analysis in accordance with an embodiment of the present invention. Figure 3B is a functional block diagram of a test system in which a method according to the present invention can be practiced. Figure 4 is a diagram illustrating a method for capturing data packets for analysis in accordance with another embodiment of the present invention. Figures 5A and 5B are functional block diagrams of
signal switching circuits for capturing data packets for conformance analysis with additional embodiments of the present invention. Figure 6 is a diagram illustrating a method for capturing data packets for analysis using the circuit of Figures 5A and 5B. Figure 7 is a diagram illustrating a method for capturing data packets for analysis using the circuit of Figures 5A and 5B. Figures 8A and 8B are diagrams illustrating additional methods for capturing data packets for analysis using the circuit of Figures 5A and 5B. DETAILED DESCRIPTION OF THE INVENTION The following detailed description refers to exemplary embodiments of the present invention with reference to the accompanying drawings. Said description is contemplated to illustrate the present invention and not to limit its scope. Such modalities are described in sufficient detail to enable a person with ordinary skill in the art to practice the present invention and it will be understood that other modalities may be practiced with certain variations without departing from the spirit and scope of the claimed invention. In the present disclosure, except if a clear indication to the contrary is provided from the context,
it will be understood that elements of individual circuits as described may be singular or plural. For example, the terms "circuit" and "or circuit set" may include either one component or several components, which are either active and / or passive and are connected or otherwise coupled together (eg, as one or several integrated circuit chips) to provide the function described. In addition, the term "signal" may refer to one or several streams, one or more voltages, or a data signal. In the drawings, the same elements or related elements will receive the same alphabetic, numeric or alphanumeric identifiers or alphabetic, numeric or alphanumeric related identifiers. Furthermore, while the present invention has been discussed in the context of implementation is using a discrete electronic circuit (preferably in the form of one or several chips of integrated circuits), the functions of any part of said circuit can be implemented alternatively using one or more Properly programmed processors, according to the signal frequencies or the data rates to be processed. With reference to Figure 1, a conventional test equipment typically operates a signal and captures data packets after an activation event of this type. After the capture of the data and its storage in memory, the data is generally transferred to a
Separate analysis circuit either within the test equipment or to a remote analysis circuit, for example, a personal computer for analysis and display of the results. For example, for a series of data packet 101-108 received from the signal source, i.e., the device under test (DUT), the duration of the capture interval 120 is typically substantially equal to the duration of a single packet of data. data. The captured data packet is transferred during the interval 130 to the analysis portion of the test equipment where it is analyzed during the interval 140 and possibly deployed. While it may be possible for the system to be available to capture additional data after the transfer interval 130, a data validity test is generally required before it can start capturing additional data, as represented by the interval 140. In any In this case, even if an additional time lapse 140 is not required, the next data capture interval 121 can not start until the termination of the analysis interval 140, which prevents the capture of closely spaced Consecutive data packets. Accordingly, it will only be possible to capture data packet 101, 105 with wide and often non-consecutive spacings due to these necessary delays. If the data packets are more spaced, such as data packets 111, 112 and
113, fewer packets will be omitted between captured packets. In addition, the capture 120, transfer 130 and analysis 140 intervals are not necessarily scaled and the data transfer interval 130 is often significantly longer than the duration of the data packet being captured. This is particularly true in the case of systems that have large bandwidth, for example, where very high data sampling rates are required, therefore requiring the collection of a large amount of data when sampling data packets yet relatively short In cases of this type, in order to analyze all the data packets, the packets must be widely spaced over time thus causing the system to operate for testing in a mode in which DUT is not normally operated. In addition, it is often desirable to capture consecutive data packets in order to analyze short-term changes in the operation of the system. Therefore, it is then necessary to increase the data capture interval. In addition, it is often desirable in production test environments to use statistical analyzes of test data to determine performance characteristics. The fact of having consecutive data packets facilitates the analysis of system variations, as for example
power control operation of a code division multiple access transmitter (CD A) where the signal strength is frequently variable. Similar power control methods are used in other forms of wireless signal communication, and it is often desirable to know if the power being analyzed is at its maximum level or at its minimum level before analyzing the data packets captured since the quality of data transmission often depends on the actual signal transmission power (ie, the compression of the signal in the transmitter frequently affects the quality of the transmitted signal). With reference to Figure 2, a convention system for capturing and analyzing consecutive data packet 201, 202, 203, 204 is based on an increased data capture interval 220 for sectioning the range that includes the desired data packets. Correspondingly, the amount of data captured will be increased by an amount equal to the captured data packets plus the time intervals between them, or spaces, by which the data packets are separated. As a result, the transfer interval 230 will also be significantly increased. In the cases in which the data packets 211, 212, 213 are more widely spaced, the capture interval
data 250 is increased by a corresponding significant amount as well as the transfer interval (not shown), thereby significantly slowing the operation of the test equipment as well as increasing the required amount of data capture memory within and, consequently, the cost of the test equipment. With reference to Figure 3A, in accordance with the presently claimed invention, several programmable activation events are used to capture the data packets, instead of using a single trigger for each data capture. For example, with closely spaced data packets 301-308, an activation sequence may be programmed in order to capture four consecutive packets 301-304 during data capture intervals 321-324. The duration of each capture interval 321-324 is preferably equal to the duration of each corresponding data pack 301-304. This advantageously groups the four data packets avoiding the capture of effectively null data associated with the time intervals between the actual data packets is 301-304. Accordingly, the transfer time 330 for the captured data is reduced. This reduced data transfer time captured 330, compared to the overall time interval during which
the incoming data packets arrive, they improve significantly since the incoming data packets 311-313 are further spaced. In other words, in the case of data packets 311-313 having durations equal to the corresponding closely spaced data packets 301-304, regardless of the longer durations of the time intervals between such data packets 311-313, the Resulting data capture intervals 321-324 remain the same (this includes the capture of an incoming data packet 314 not illustrated due to space limitations in the drawing), as well as the data transfer interval 330. However, in comparison with the overall time required for incoming data packets 311-314 to arrive, the data transfer interval 330 is significantly reduced. Either way, regardless of whether the incoming data packets are closely spaced or widely spaced, the data transfer time can be used and remains independent of the time interval for the stream of incoming data packets. With reference to Figure 3B, an example of a system 360 for capturing data packets for analysis in accordance with the present invention includes a data capture circuit 362 (e.g., a sampling and retention circuit and a data conversion circuit). analog signals to signals
digital) to capture the incoming data stream 361. The captured data 363 is stored in the memory 364. The control circuit 366 controls the capture circuit 362 and the memory 364 through control signals 366a, 366b. The captured data 365 is retrieved from the memory 364 and transferred to the analysis circuit 368 (e.g., a microprocessor and associated support circuit), either locally within the test equipment or remotely on an external computer, all of which are well known in the art. The results 367 of the data analysis can then be made available for viewing in a 370 display by the user (not illustrated). In normal operation, the data packets tend to be separated during longer time intervals than those typically used for production testing since it is desirable to minimize the time required for said test. However, this can result in test results that are not really indicators of circuit operation during normal use. One way to resolve this situation is to further reduce the data transfer intervals 330 and data analysis 340 (Figure 3A) compared to the time interval required for the arrival of the incoming data packets 301-304. In many cases, it may be necessary to capture each entire data packet. For example, in the data standard
Wireless IEEE 802.11a, it is specified that the quality of the transmission must be measured at a minimum of 16 data symbols. While data packets are generally larger than 16 symbols, it is only necessary to capture 16 symbols from each packet to perform the test in accordance with the standard. Another option is to measure the power of orthogonal frequency division multiplexing (OFDM) signals according to the standard. The RMS power can be measured by measuring the training symbol of the data packet (for example, typically, 8-16 microseconds in the packet), thus requiring the capture of only 16 microseconds of each data packet for measurement of power. With reference to Figure 4, this could be done by capturing selected portions 411-414 of the incoming data packets 401-404 during corresponding data capture intervals 421-424. By reducing the capture time in this manner, the amount of data captured for the four consecutive data packets 421-424 will be reduced, particularly when this captured data is packed consecutively before the data transfer interval 430. Thus similarly, the data analysis interval 440 will also be reduced. Alternatively, in addition to the captured data 421-424, small packets of data separators 471-474 may be
entered after each corresponding portion of captured data. This can have the effect of simplifying a subsequent analysis of the data since the system can more easily identify the start or end of each portion 421-424 of captured data. The additional general data to be transferred, as a result of this, will depend on the size of the data separator packets 471-474. As a further alternative, unlike inserting packets of separators 421-424, the captured data may also be encoded with a marker signal, for example, as the least significant bit of the captured data or in a separate data bit. This can reduce or even eliminate the additional general data introduced in another way by the data separator packages 471-472. Another advantage of using limited data capture times is related to the capture of multiple data packets. For example, when multiple data packets are captured, each packet of data in the stream may be different. The capture of multiple data packets allows the capture, in a single capture frequency, of one of each type of data packet used. This can usefully reduce the test time since all the results for a single frequency can be obtained
in a single frequency of data capture. In addition, the analysis of the captured data can be optimized by reducing the data for each packet so that it is equal to the longer required data capture. For example, the transmission of multiple data packets may result in the transmission of packets of different lengths, since the controllers used to produce the packets may employ a fixed amount of data per packet, with the durations becoming longer with speeds of lower data, However, even if the duration becomes longer, only the predetermined capture time has to be used, for example, the first 16 symbols in the case of a system based on the IEEE 802.11a OFDM standard while the symbol frequency remains constant, the modulation used for this symbol will change the data rate, as is commonly done in order to simplify the implementations. Using a fixed capture time for each data packet can significantly improve the analysis of multiple data packets. In the comments above, it has been considered that the system is activated at the beginning of each data packet. However, it will be understood that a predetermined delay can be introduced into the drive in order to initiate data capture at a later point in each packet of data.
data. For example, in an IEEE 802.11a OFDM signal, when it is sought to capture data of eight to 16 microseconds within the data packet, a delay of eight microseconds may be introduced in order to delay the activation of the data capture. When testing multiple transmitters in a MIMO system, it may be desirable to use multiple receivers in parallel in such a way that the data packets can be captured and analyzed in parallel. However, a test equipment that has receivers in parallel can be excessively expensive for production tests. An alternative to the need for parallel testing is the use of a composite signal analysis as proposed in the US Provisional Patent Application No. 60/596, 444, filed on September 23, 2005 and entitled "Method for Simultaneous Testing of Multiple Orthogonal Frequency Division Multiplexed Transmitters with Single Vector Signal Analyzer "[Method for simultaneously testing multiple transmitters multiplexed by orthogonal frequency division with a single vector signal analyzer], the disclosure of which is incorporated herein by reference. Said composite analysis includes the combination of multiple transmission signals in a single signal, for example, by means of a signal power combiner in such a way that a single receiver can be used to analyze the
composite signal Said compound signal analysis technique requires a certain method through which the connection between the transmitters can be identified or analyzed in order to determine the origin of the analyzed signal. In addition, it is important that the data within the package being analyzed is known. While this is most easily accomplished in a production test environment, it nevertheless requires special controllers for the transmitter. In accordance with another embodiment of the present invention, these aspects can be solved by introducing a signal switching circuit to isolate the individual transmitter signals for analysis. This will allow testing the connection between the transmitters and, in cases where the connection is not significant, will allow error vector magnitude (EVM) measurements for data packets transmitted individually from the individual transmitters. However, the simple introduction of switching circuit will probably affect the test time, since after the capture of one or several data packets from a transmitter a certain delay will be introduced as the switches provide the transmission of the signal to from another transmitter. Such delays can be significant, depending on the production test environment.
With reference to Figures 5A and 5B, test problems associated with such delays can be minimized or eruded using one of the switching systems or both switching systems. (These examples offer switching between three transmitter inputs 501, 502, 503, however it will be understood that these implementations can be extended to handle additional input signals.) This circuit includes a power combiner 530 to combine several input signals 501 , 502, 503, received through respective signal switches 521, 522, 523, in a single signal 540 that will be fed to the test equipment. Such signal switches 251, 522, 523 are well known in the art and have fast switching times, for example, in comparison to signal frequencies and data rates. In addition, such signal switches 521, 522, 523 are preferably solid state switches and can be implemented as multiple switches in series or parallel, as necessary or desired to provide desired isolation between two transmitters (not shown) and the power combiner 530, as well as appropriate determination impedance in order to allow the power combiner 530 to correctly sum the different input signals. With reference to Figure 5A, this implementation includes signal power detectors 511, 512, 513 to detect
the power of the respective input signals 501, 502, 503, with power signals detected by being provided to a control circle 550, which offers control signals for the input signal switches 521, 522, 523. This allows the service control 550 determines the presence of a signal (eg, based on a quantity of power indicated by the power detection signal) at each of the input terminals. Based on these power indication signals, as well as the known (e.g., open or closed) states of the switches 521, 522, 523, the control circuit 150 generates an activation signal 550 (e.g., based on a programmable state machine within the control circuit 550) for controlling the capture by the test equipment (not shown) of the data packets received in the output signal 540 of the power combiner 530, as discussed above. Alternatively, a single detector can be used, for example, the first signal power detector 511 for the first received signal 501. With all the DUT transmitters simultaneously operating in a similar manner, the detection by this unique detector 511 of the arrival of the packet The data in the first received signal 501 also indicates the arrival of the data packets in the remaining received signals 502, 503. With reference to Figure 5B, according to an implementation
Alternatively, a single power detector 514 is used in place of multiple input power detectors 511, 512, 513 to detect the power of the output signal 540 of the power combiner 530, as before, the control circuit 550 knows the states of the input switches 521, 522, 523 and can then determine which input signal 501, 502, 503 is providing the output signal 540 through the power combiner 530. While they differ in their respective implementations, both Circuits of Figures 5A and 5B offer the switching capability to input the input signals 501, 502, 503 in a known sequence during the time intervals between the respective data packets of the signals being tested. Accordingly, switching may occur after the capture of each data packet, after the capture of multiple data packets, or after the capture of the desired amount of data (for example, after the capture of the first 16 data packets). desired symbols of a pack of 32 symbols), as desired. With reference to Figure 6, a possible method of operation of such a system includes the transmission of a stream of data packets 601-608, with each of the three transmitters transmitting a respective data stream 601a-608a, 601b 608b, 601c-608c. The control circuit 550 (Figure 5A and 5B) selects the first output of
transmitter 601a, followed by second transmitter output 602b, and transmitter third 603c. This is then followed by a selection of the outputs of the three transmitters 604a, 604b, 604c which are combined into a composite signal. Multiple activation is used as discussed above in order to reduce the amount of data actually captured, for example, the data capture intervals 621, 622, 623, 624 have to be only long enough to capture the desired amounts of each one of the individual data packets 601a, 602b, 603c, and the sum of the data packets 604a, 604b, 604c. as discussed above, these data are combined, for example, packaged at a captured data rate 621-624, transferred during a transfer interval 630, and analyzed during a 640 analysis interval. Switching control signals 651, 652 , 653, for the three signal switches 521, 522, 523 are also shown, in the manner produced by the control circuit 550. Alternatively, instead of capturing the data packet portions that are internally controlled by the test instrument same, the activation signal 660 provided by the control circuit 550 can be used. This can be helpful when multiple input signals are involved, such as
when testing a MIMO system. This activation signal 660 identifies the data packet capture intervals 621, 622, 623, 624 (for example, when a high signal level corresponds to the data capture interval). The angle portion of the signal 670 at the end identifies an optional end of activation sequence that allows the test instrument to complete its capture of data packets and initiate data transfer, i.e., during the transfer interval 630. Alternatively, the data transfer interval 630 may be started after the capture of the desired amount of data packets, for example, four data packets as shown in this example. As indicated, the control of the activation of the data packet capture with the control circuit 550 can be of use. For example, when testing a MIMO system, the order of the data packets can be controlled, thus ensuring that the first packet is from the first transmitter, the second packet is from the second transmitter, the third packet is from the third transmitter, and The last data captured is the combined signal of all the transmitters. Control of data capture with such an activation signal will not introduce problematic delays since the receiver circuit within the test equipment will typically use a high-speed analog-to-digital converter having a design of
line where the delay (ie, through the line) is significantly greater than the time required for the analog trigger signal to start capturing the data. In the case where the activation signal is derived digitally, a simple memory circuit or digital memory can be used to store the history of the signal in order to ensure an appropriate timing. With reference to Figure 7, an alternative use of the control circuit 550 to generate the activation 760 includes capturing small portions 711, 712, 713 of the respective data packets 701a. 702b, 703c, while still capturing a larger portion 714 of the combined data packets 704a, 704b, 704c. This will provide sufficient data capture to measure EVM of the first portions of the packets sent by the different transmitters while maintaining the longer data packets in order to allow sufficient data capture in the case of the four data packets combined 704a, 704b, 704c, to allow accurate spectral mask measurements. As a result, the captured data 721, 722, 723, 724, when packaged for transfer during the transfer interval 730, are significantly shorter. Since the control circuit 550 controls the different switches, it can be easily programmed to control the duration of the capture intervals in such a way that the
capture of the portions 711, 712, 713 of the individual packets 701a, 702b, 703c may be different, for example, more pictures than the range required to capture the potion 714 of the combined data packets 704a, 704b, 704c. When testing a MIMO system, it may be necessary to use external hardware to synchronize the duration of data capture with the respective switch states (on and off), since the test equipment may not know when the packet type appropriate is being transmitted. However, it is also possible to introduce that type of synchronization within the test equipment when testing a signal transmitter. For example, it may be desirable to perform multiple power measurements for an IEEE 802.11 signal to OFDM, followed by a spectral mask measurement. As mentioned above, the power measurement may require only 6.4 microseconds, for example, two consecutive intervals of 3.2 microseconds starting 8.8 microseconds after the start and ending 0.8 microseconds before the end of the 16 microsecond data packet preamble, while A spectral mask measurement may require a longer capture interval in order to provide a reasonable average power. Either way, said timing synchronization can be
implemented in any manner well known in the art. As indicated above in the discussion of the switching circuit (Figure 5A and 5B), it can be difficult to test the insulation between the transmitters when testing composite signals. This test of composite signals allows the power test of individual transmitters, but the use of a signal combiner generally complicates the identification of the origin of the power that is being measured and sometimes makes it impossible. By adding switches to the output of the power combiner, it becomes possible to measure the connection to the extent that the insulation between the switches is better than the coupling level being tested. With reference to Figure 8A, the use of a data packet testing technique as discussed above when testing a MIMO system can be described as follows: during the transmission of the first data packet 801, the packet 801a from the The first transmitter is transported to the power combiner 530 (Figure 5A and 5B). Similarly, during the transmission of the second data packet 802 and the third data packet 803, the data packets 802b, 803c from the second transmitter and the third transmitter are transported to the power combiner 530. The appropriate switching environments are achieved using the three control signals
switch 851, 852, 853. The capture of the desired portions 811, 812, 813 of the data packets 801a, 802b, 803c is effected during the time slots 821, 822, 823 in accordance with the activation control signal 860. The data packet signal acquired during the first interval 821 contains the power attributable only to the first transmitter. This capture interval is relatively short since the power connection can be measured through composite measurement methods in the long, high performance (HT-LTS) training sequence that appears at the beginning of the data packet. During the second capture interval 822, the captured signal includes primarily power from the second transmitter, but also some additional power from the data packet connection of the first transmitter 802a in the second transmitter with DUT. Using the techniques of power analysis and composite measurement (in accordance with that commented in the application No. 60 / 596,444, as indicated above), the power attributed to the data packet of the first transmitter 802a can be determined. Similarly, after the capture of the third data packet 803c during its data capture interval 823, the power allocated to the data packet of the first transmitter 803a can also be determined. Similarly, during the first data capture interval 821, it can be determined
the power connection allocated to the data packet of the second transmitter 801b and data packet of the third transmitter 801c, as well as the power allocated to the data packet of the first transmitter 802a and third transmitter data pack 802c after the second capture interval of data 822. Therefore, the transmitter power attributed to the transmitter of interest as well as the contributions of the other transmitters can be determined. Referring again to Figure 7, it will be understood that the desired information on the data transmission characteristics may be obtained during the first three data signal capture intervals 721, 722, 723, since the connection between the transmitters may be be determined, and the last data capture interval 724 may be used to measure the quality of signal transmission and other parameters using the composite EVM techniques in accordance with that described in Application No. 60 / 595,444, as indicated above. With reference to Figure 8B, it will further be understood that, as an alternative, intermediate packets 802, 803, 805, 806 between the captured packets 801, 804, 807 may be skipped. For example, it may be necessary to allow the settling of the transmitter being tested, in terms of frequency and power. This can be implemented by simply counting the number of packages that are measured before starting the
capture of data packets. This is particularly useful when testing multiple packages. For example, it may be desirable to transmit different power levels for calibration purposes or other tests. If the transmitter requires some time for settlement, a first number of packets can be transmitted at a power level, after which the power level changes and a second number of packets is transmitted. In such cases, it may be desirable to transmit the majority of such packets before capturing one or more of these packets at the end before the power level change for the next transmission of data packets. Various other modifications and alterations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and spirit of the invention. Although the invention has been described in relation to specific preferred embodiments, it will be understood that the claimed invention is not unduly limited to such specific modalities. It is contemplated that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents are covered by them.