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d'Antras et al., 2017 - Google Patents

Low overhead dynamic binary translation on arm

d'Antras et al., 2017

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Document ID
3392875001815395736
Author
d'Antras A
Gorgovan C
Garside J
Luján M
Publication year
Publication venue
Proceedings of the 38th ACM SIGPLAN Conference on Programming Language Design and Implementation

External Links

Snippet

The ARMv8 architecture introduced AArch64, a 64-bit execution mode with a new instruction set, while retaining binary compatibility with previous versions of the ARM architecture through AArch32, a 32-bit execution mode. Most hardware implementations of ARMv8 …
Continue reading at research.manchester.ac.uk (PDF) (other versions)

Classifications

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    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
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