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Choi, 2019 - Google Patents

Performance Debugging Frameworks for FPGA High-Level Synthesis

Choi, 2019

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Document ID
3390655411469838037
Author
Choi Y
Publication year

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Snippet

Using high-level synthesis (HLS) tools for field-programmable gate array (FPGA) design is becoming an increasingly popular choice because HLS tools can generate a high-quality design in a short development time. However, current HLS tools still cannot adequately …
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Classifications

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