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Akkaş et al., 2006 - Google Patents

Dual-mode floating-point multiplier architectures with parallel operations

Akkaş et al., 2006

Document ID
3093816412026065897
Author
Akkaş A
Schulte M
Publication year
Publication venue
Journal of Systems Architecture

External Links

Snippet

Although most modern processors have hardware support for double precision or double- extended precision floating-point multiplication, this support is inadequate for many scientific computations. This paper presents the architecture of a quadruple precision floating-point …
Continue reading at www.sciencedirect.com (other versions)

Classifications

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    • G06F7/52—Multiplying; Dividing
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