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Patel et al., 2006 - Google Patents

A scalable FPGA-based multiprocessor

Patel et al., 2006

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Document ID
2763171549780618864
Author
Patel A
Madill C
Saldana M
Comis C
Pomes R
Chow P
Publication year
Publication venue
2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

External Links

Snippet

It has been shown that a small number of FPGAs can significantly accelerate certain computing tasks by up to two or three orders of magnitude. However, particularly intensive large-scale computing applications, such as molecular dynamics simulations of biological …
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Classifications

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    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17381—Two dimensional, e.g. mesh, torus
    • G—PHYSICS
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    • G06F15/8007—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
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    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
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