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Huang et al., 2004 - Google Patents

Forward-looking macro generation and relational placement during high level synthesis to FPGAs

Huang et al., 2004

Document ID
276957414660343761
Author
Huang R
Vemuri R
Publication year
Publication venue
18th International Parallel and Distributed Processing Symposium, 2004. Proceedings.

External Links

Snippet

Summary form only given. Incorporating physical information into earlier architectural and logic synthesis stages is highly desirable since it allows more realistic exploration of the design space and the generation of solutions with predictable metrics. We present a forward …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
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    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
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