[go: up one dir, main page]

Wang et al., 1999 - Google Patents

Design and implementation of fault-tolerant and cost effective crossbar switches for multiprocessor systems

Wang et al., 1999

View PDF
Document ID
26804394166659241
Author
Wang K
Wu C
Publication year
Publication venue
IEE Proceedings-Computers and Digital Techniques

External Links

Snippet

Two general crossbar switch models are proposed: the modified one-sided crossbar switch and the ripple K one-sided crossbar switch. They both balance cost and reliability, where cost is expressed in terms of crosspoint count or area. The two-sided crossbar switch and …
Continue reading at ir.lib.nycu.edu.tw (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored programme computers
    • G06F15/80—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored programme computers
    • G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding through a switch fabric
    • H04L49/253—Connections establishment or release between ports
    • H04L49/254—Centralized controller, i.e. arbitration or scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H04L49/1553—Interconnection of ATM switching modules, e.g. ATM switching fabrics
    • H04L49/1561—Distribute and route fabrics, e.g. Batcher-Banyan

Similar Documents

Publication Publication Date Title
Siegel et al. The multistage cube: A versatile interconnection network
Rettberg et al. The Monarch parallel processor hardware design
Zhang et al. A reconfigurable routing algorithm for a fault-tolerant 2D-mesh network-on-chip
US7434191B2 (en) Router
US5630162A (en) Array processor dotted communication network based on H-DOTs
Balkan et al. A mesh-of-trees interconnection network for single-chip parallel processing
WO2012119533A1 (en) High-end fault-tolerant computer system and method for same
Balkan et al. Mesh-of-trees and alternative interconnection networks for single-chip parallelism
Wang et al. Design and implementation of fault-tolerant and cost effective crossbar switches for multiprocessor systems
CN112987900B (en) Multi-path server and multi-path server signal interconnection system
Khodwe et al. VHDL Implementation Of Reconfigurable Crossbar Switch For Binoc Router
Bistouni et al. Reliability analysis of multilayer multistage interconnection networks
Balkan et al. An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing
Requena et al. Exploiting wiring resources on interconnection network: increasing path diversity
Yang et al. Communication performance in multiple-bus systems
Rezaei et al. Fault-tolerant 3-D network-on-chip design using dynamic link sharing
Li et al. Routability improvement using dynamic interconnect architecture
Bouhraoua et al. Improved modified fat-tree topology network-on-chip
JP2525117B2 (en) Array processor
Saravanakumar et al. Implementation of scheduling algorithms for on chip communications
Minsky et al. RN1: Low-latency, dilated, crossbar router
Lee A virtual bus architecture for dynamic parallel processing
Wang et al. Meshed bluetree: Time-predictable multimemory interconnect for multicore architectures
Marvasti et al. An analysis of hypermesh nocs in fpgas
Oruç One-sided binary tree-crossbar switching for on-chip networks