Chan et al., 2019 - Google Patents
Yield Learning Methodologies and Failure Isolation in Ring Oscillator Circuit for CMOS Technology ResearchChan et al., 2019
View PDF- Document ID
- 2454712198480915924
- Author
- Chan V
- Bergendahl M
- Lea D
- Strane J
- Austin B
- Boye C
- Mattam S
- Choi S
- Gaul A
- Cheng K
- Greene A
- Levin T
- Teehan S
- Karve G
- Guo D
- Publication year
- Publication venue
- IEEE Transactions on Semiconductor Manufacturing
External Links
Snippet
We detail the use of ring oscillators (ROs) for yield learning during the research phase of a CMOS technology generation. Failing circuits are located and classified based on electrical analysis of ROs and FETs (Field Effect Transistor) wired out from RO environments. Based …
- 238000000034 method 0 title abstract description 34
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/302—Contactless testing
- G01R31/308—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation
- G01R31/311—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation of integrated circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31718—Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. varying supply voltage
- G01R31/3004—Current or voltage test
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
- G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Bhushan et al. | Ring oscillators for CMOS process tuning and variability control | |
| Teo et al. | TCAD-enabled machine learning defect prediction to accelerate advanced semiconductor device failure analysis | |
| Orbon et al. | Integrated electrical and SEM-based defect characterization for rapid yield ramp | |
| US20170154687A1 (en) | Sram-like ebi structure design and implementation to capture mosfet source-drain leakage eariler | |
| EP2439549B1 (en) | Non-destructive determination of functionality of an unknown semiconductor device | |
| Yamamoto et al. | Development of a large-scale TEG for evaluation and analysis of yield and variation | |
| Chan et al. | Yield Learning Methodologies and Failure Isolation in Ring Oscillator Circuit for CMOS Technology Research | |
| Quah et al. | Static fault localization of subtle metallization defects using near infrared photon emission microscopy | |
| Doong et al. | Field-configurable test structure array (FC-TSA): Enabling design for monitor, model, and manufacturability | |
| TW201923373A (en) | Electron beam probing for chip debug and fault isolation | |
| Chan et al. | Ring oscillator yield learning methodologies for CMOS technology research | |
| Chan et al. | Failure isolation in ring oscillator circuit and defect detection in CMOS technology research | |
| US7111257B2 (en) | Using a partial metal level mask for early test results | |
| US20180226303A1 (en) | Method of manufacturing semiconductor device | |
| Faraby et al. | Efficient fault isolation and failure analysis methods to root cause defects in microprocessors | |
| JP2011210775A (en) | Manufacturing method of semiconductor device | |
| Lam et al. | DFI filler cells–new embedded type of test structures for non-contact detection of electrical defects on product wafers | |
| US7151387B2 (en) | Analysis module, integrated circuit, system and method for testing an integrated circuit | |
| US6653849B1 (en) | IC analysis involving logic state mapping in a SOI die | |
| Burmer et al. | Failure analyses for debug and ramp-up of modern IC’s | |
| Chuang et al. | Conductive atomic force microscopy application on leaky contact analysis and characterization | |
| US20250231233A1 (en) | Repackaging ic chip for fault identification | |
| Brozek et al. | Product Design Enhancement With Test Structures for Non-Contact Detection of Yield Detractors | |
| Veendrick | Failure Analysis | |
| Ting et al. | Failure analysis on capacitor failures using simple circuit edit passive voltage contrast method |