[go: up one dir, main page]

Naviner et al., 2011 - Google Patents

FIFA: A fault-injection–fault-analysis-based tool for reliability assessment at RTL level

Naviner et al., 2011

Document ID
2433973141636270537
Author
Naviner L
Naviner J
dos Santos Jr G
Marques E
Paiva Jr N
Publication year
Publication venue
Microelectronics Reliability

External Links

Snippet

This paper presents an efficient platform for fault robustness estimation of digital circuits. The proposed platform, named FIFA, was designed as a hardware IP to accelerate the Fault Injection and Fault masking Analysis approach. It supports several fault models as well as …
Continue reading at www.sciencedirect.com (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5022Logic simulation, e.g. for logic circuit operation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081Layout analysis, e.g. layout verification, design rule check
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5036Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/5054Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3183Generation of test inputs, e.g. test vectors, patterns or sequence
    • G01R31/318385Random or pseudo-random test pattern
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Preventing errors by testing or debugging software
    • G06F11/3668Software testing
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70Fault tolerant, i.e. transient fault suppression
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832Specific tests of electronic circuits not provided for elsewhere
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled

Similar Documents

Publication Publication Date Title
Naviner et al. FIFA: A fault-injection–fault-analysis-based tool for reliability assessment at RTL level
US8108728B2 (en) Method and apparatus for operational-level functional and degradation fault analysis
US7302656B2 (en) Method and system for performing functional verification of logic circuits
Pramanick et al. On the fault coverage of gate delay fault detecting tests
Ashraf et al. Design-for-diversity for improved fault-tolerance of TMR systems on FPGAs
Devarajegowda et al. Formal verification methodology in an industrial setup
Letychevskyi et al. Modeling method for development of digital system algorithms based on programmable logic devices
US10768227B2 (en) Systems and methods for analyzing failure rates due to soft/hard errors in the design of a digital electronic device
US7124383B2 (en) Integrated proof flow system and method
US20170083651A1 (en) Equivalence checking of analog models
US8453082B2 (en) Soft error verification in hardware designs
US10380301B1 (en) Method for waveform based debugging for cover failures from formal verification
US9632894B2 (en) Apparatus for error simulation and method thereof
US20050144580A1 (en) Method and system for testing a logic design
Metra et al. On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits
Feng et al. IPR: in-place reconfiguration for FPGA fault tolerance?
US20240184967A1 (en) Focused testing and verification of circuit designs using hardware description language simulation
Lu et al. Model-based design, analysis and assessment framework for safety-critical systems
US7080333B1 (en) Verifying logic synthesizers
US10268786B2 (en) System and method for capturing transaction specific stage-wise log data
Hung et al. Faster FPGA debug: Efficiently coupling trace instruments with user circuitry
US7051303B1 (en) Method and apparatus for detection and isolation during large scale circuit verification
US9098637B1 (en) Ranking process for simulation-based functional verification
US7047173B1 (en) Analog signal verification using digital signatures
Raik et al. Code coverage analysis using high-level decision diagrams