[go: up one dir, main page]

Kishore et al., 2018 - Google Patents

Design and comparative analysis of inexact speculative adder and multiplier

Kishore et al., 2018

View PDF
Document ID
2226841840841090433
Author
Kishore K
Prasad B
Teja Y
Akhila D
Sai K
Kumar P
Publication year
Publication venue
International Journal of Engineering and Technology (UAE), ISSN No

External Links

Snippet

A Carry look ahead adder is a sort of the summer used in the logic design of the digital systems. The CLA boost up the speed by decreasing the measure of duration needed to calculate the carry bits. The CLA based outline of the inexact speculative adder is pipelined …
Continue reading at www.academia.edu (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/505Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
    • G06F7/523Multiplying only
    • G06F7/53Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
    • G06F7/523Multiplying only
    • G06F7/533Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443Sum of products
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499Denomination or exception handling, e.g. rounding, overflow
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804Details

Similar Documents

Publication Publication Date Title
Kishore et al. Design and comparative analysis of inexact speculative adder and multiplier
US6205458B1 (en) Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith
Lin et al. High-performance low-power carry speculative addition with variable latency
Camus et al. Energy-efficient inexact speculative adder with high performance and accuracy control
Di et al. Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design
US9146707B2 (en) Generating a fast 3x multiplicand term for radix-8 booth multiplication
Jothin et al. High performance significance approximation error tolerance adder for image processing applications
Nikhil et al. Design of low power barrel shifter and vedic multiplier with kogge-stone adder using reversible logic gates
Cui et al. Design of high-speed wide-word hybrid parallel-prefix/carry-select and skip adders
Saranya Low power and area-efficient carry select adder
Shrestha High-speed and low-power VLSI-architecture for inexact speculative adder
US7739324B1 (en) Timing driven synthesis of sum-of-product functional blocks
Deb et al. High-speed comparator architectures for fast binary comparison
Rashidi et al. Design of a low-power and low-cost booth-shift/add multiplexer-based multiplier
Yagain et al. Design of High‐Speed Adders for Efficient Digital Design Blocks
Nithya et al. Design of Delay Efficient Hybrid Adder for High Speed Applications
Gottem et al. High Speed Approximate Carry Speculative Adder in Error Tolerance Applications
Sukla et al. Low-power and area efficient approximate multiplier with reduced partial products
KV et al. ASIC Design and Implementation of 32 Bit Arithmetic and Logic Unit.
Kandula et al. Performance Analysis of VLSI Architecture of Dadda Multiplier Using Divide and Conquer Strategy with Approximate Adders
Vani et al. VLSI design of a novel area efficient fir filter design using roba multiplier
Gottem et al. A Critical Analysis of Approximate Adders: Correctness and Analysis of Performance
Medasani et al. 16-bit Vedic multiplier Using Carry Skip Adder
Ashok Chaitanya Varma et al. High-Throughput VLSI Architectures for CRC-16 computation in VLSI signal processing
Sarraf et al. High-Speed Energy-Efficient Canny-Edge Detector Using Novel Approximate Adder