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Baskaran et al., 2022 - Google Patents

An architecture interface and offload model for low-overhead, near-data, distributed accelerators

Baskaran et al., 2022

View PDF
Document ID
215672934148419159
Author
Baskaran S
Kandemir M
Sampson J
Publication year
Publication venue
2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)

External Links

Snippet

The performance and energy costs of coordinating and performing data movement have led to proposals adding compute units and/or specialized access units to the memory hierarchy. However, current on-chip offload models are restricted to fixed compute and access pattern …
Continue reading at par.nsf.gov (PDF) (other versions)

Classifications

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    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G06F9/3891—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
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