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Vanderbauwhede et al., 2018 - Google Patents

MORA: High-Level FPGA Programming Using a Many-Core Framework

Vanderbauwhede et al., 2018

Document ID
1914422815682577513
Author
Vanderbauwhede W
Chalamalasetti S
Margala M
Publication year
Publication venue
Multicore Technology

External Links

Snippet

Department of Electrical and Computer Engineering, University of Massachusetts, Lowell, MA, USA1. 1 Overview of the State of the Art in High-Level FPGA Programming........................ ............................ 41.2 Introduction to the MORA Framework.......................... 6 1.2. 1 MORA …
Continue reading at www.taylorfrancis.com (other versions)

Classifications

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    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
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    • G06F9/3895—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
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    • G06F9/3891—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
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