Teifel et al., 2004 - Google Patents
Highly pipelined asynchronous FPGAsTeifel et al., 2004
View PDF- Document ID
- 18221488619529685184
- Author
- Teifel J
- Manohar R
- Publication year
- Publication venue
- proceedings of the 2004 ACM/SIGDA 12th International symposium on field programmable gate arrays
External Links
Snippet
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and show how asynchronous logic can efficiently take advantage of this large amount of …
- 238000000034 method 0 abstract description 31
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Teifel et al. | Highly pipelined asynchronous FPGAs | |
| Teifel et al. | An asynchronous dataflow FPGA architecture | |
| US7157934B2 (en) | Programmable asynchronous pipeline arrays | |
| Singh et al. | PITIA: an FPGA for throughput-intensive applications | |
| Singh et al. | Interconnect pipelining in a throughput-intensive FPGA architecture | |
| US6867620B2 (en) | Circuits and methods for high-capacity asynchronous pipeline | |
| Compton et al. | An introduction to reconfigurable computing | |
| US8453079B2 (en) | Automated conversion of synchronous to asynchronous circuit design representations | |
| Kaviani et al. | Computational field programmable architecture | |
| Phillips et al. | Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip | |
| Wong et al. | An architecture for asynchronous FPGAs | |
| Beerel et al. | Low power and energy efficient asynchronous design | |
| Sparso et al. | Design and performance analysis of delay insensitive multi-ring structures | |
| Peng et al. | Automated synthesis for asynchronous FPGAs | |
| Sotiriou et al. | De-synchronization: Asynchronous circuits from synchronous specifications | |
| Smit et al. | Low cost & fast turnaround: Reconfigurable graph-based execution units | |
| Garnica et al. | Fine-grain asynchronous circuits for low-power high performance DSP implementations | |
| US20250348642A1 (en) | Content compute processors and architectures | |
| Chin | Architectures and tools for efficient reconfigurable computing | |
| Teifel | Fast prototyping of asynchronous logic | |
| Warrier et al. | Reconfigurable DSP block design for dynamically reconfigurable architecture | |
| Lallet et al. | xMAML: A modeling language for dynamically reconfigurable architectures | |
| Kujoth et al. | A reconfigurable unit for a clustered programmable-reconfigurable processor | |
| Fawaz et al. | Implementation of Highly Pipelined Datapaths on a Reconfigurable Asynchronous Substrate | |
| Satou et al. | An embedded reconfigurable logic core based on variable grain logic cell architecture |