[go: up one dir, main page]

Beringuier-Boher et al., 2013 - Google Patents

Increasing the security level of analog IPs by using a dedicated vulnerability analysis methodology

Beringuier-Boher et al., 2013

Document ID
18218929849974971431
Author
Beringuier-Boher N
Hely D
Beroulle V
Damiens J
Candelier P
Publication year
Publication venue
International Symposium on Quality Electronic Design (ISQED)

External Links

Snippet

With the increasing diffusion of multi-purpose systems such as smart phones and set-top boxes, security requirements are becoming as important as power consumption and silicon area constraints in SoCs and ASICs conception. In the same time, the complexity of IPs and …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594Timing aspects
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31727Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3177Testing of logic operation, e.g. by logic analysers
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31708Analysis of signal quality
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/74Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information operating in dual or compartmented mode, i.e. at least one secure mode

Similar Documents

Publication Publication Date Title
Jin et al. Cycle-accurate information assurance by proof-carrying based signal sensitivity tracing
US12204685B2 (en) Security property-driven vulnerability assessments of ICs against fault-injection attacks
Kison et al. Security implications of intentional capacitive crosstalk
Vosatka Introduction to hardware trojans
Proulx et al. A survey on FPGA cybersecurity design strategies
Aftabjahani et al. Special session: Cad for hardware security-automation is key to adoption of solutions
Sumathi et al. A review on HT attacks in PLD and ASIC designs with potential defence solutions
Tehranipoor et al. Secure physical design
Hu et al. Imprecise security: quality and complexity tradeoffs for hardware information flow tracking
Kareem et al. Physical unclonable functions based hardware obfuscation techniques: A state of the art
Farahmandi et al. CAD for hardware security
Tehranipoor et al. Hardware Security
Plusquellic et al. Detecting hardware Trojans using delay analysis
Beringuier-Boher et al. Increasing the security level of analog IPs by using a dedicated vulnerability analysis methodology
Marotta et al. Characterizing and Modeling Synchronous Clock-Glitch Fault Injection
Marchand et al. Low‐level implementation and side‐channel detection of stealthy hardware trojans on field programmable gate arrays
Portillo et al. Building trust in 3PIP using asset-based security property verification
Awal et al. Impedance leakage vulnerability and its utilization in reverse-engineering embedded software
Guazzelli et al. Trojan detection test for clockless circuits
Shuvo et al. Flat: Layout-aware and security property-assisted timing fault-injection attack assessment
Sunkavilli et al. FPGA security: Security threats from untrusted FPGA CAD toolchain
Wang et al. Toward a formal and quantitative evaluation framework for circuit obfuscation methods
Feiten et al. Implementation of Delay-Based PUFs on Altera FPGAs
Guilley et al. Global faults on cryptographic circuits
Nahiyan et al. Security rule check