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Toi et al., 2010 - Google Patents

High-level synthesis challenges for mapping a complete program on a dynamically reconfigurable processor

Toi et al., 2010

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Document ID
17956207057092348553
Author
Toi T
Nakamura N
Kato Y
Awashima T
Wakabayashi K
Publication year
Publication venue
IPSJ Transactions on System and LSI Design Methodology

External Links

Snippet

This paper presents a high-level synthesizer to map a complete program efficiently on a dynamically reconfigurable processor (DRP). Initially, we introduce our DRP architecture, which is suitable for control-intensive programs since it has a stand-alone finite state …
Continue reading at www.jstage.jst.go.jp (PDF) (other versions)

Classifications

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    • G06F17/50—Computer-aided design
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    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
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    • G06F9/3895—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
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