Alsafrjalani et al., 2018 - Google Patents
Tasat: Thermal-aware scheduling and tuning algorithm for heterogeneous and configurable embedded systemsAlsafrjalani et al., 2018
View PDF- Document ID
- 17829534401754619105
- Author
- Alsafrjalani M
- Adegbija T
- Publication year
- Publication venue
- Proceedings of the 2018 Great Lakes Symposium on VLSI
External Links
Snippet
Heterogeneous and configurable systems (HaCS) have been widely used to meet stringent runtime performance and energy constraints in embedded systems. However, no prior work has addressed the emerging runtime thermal constraints in these systems. To leverage …
- 238000000034 method 0 description 20
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
- G06F1/3234—Action, measure or step performed to reduce power consumption
- G06F1/324—Power saving by lowering clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5094—Allocation of resources, e.g. of the central processing unit [CPU] where the allocation takes into account power or heat criteria
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06Q—DATA PROCESSING SYSTEMS OR METHODS, SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES, NOT OTHERWISE PROVIDED FOR
- G06Q10/00—Administration; Management
- G06Q10/06—Resources, workflows, human or project management, e.g. organising, planning, scheduling or allocating time, human or machine resources; Enterprise planning; Organisational models
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Cazorla et al. | Predictable performance in SMT processors: Synergy between the OS and SMTs | |
Alsafrjalani et al. | Tasat: Thermal-aware scheduling and tuning algorithm for heterogeneous and configurable embedded systems | |
Mei et al. | Energy-aware task scheduling in heterogeneous computing environments | |
Mei et al. | Energy-aware scheduling algorithm with duplication on heterogeneous computing systems | |
Ranjbar et al. | Power-aware runtime scheduler for mixed-criticality systems on multicore platform | |
Wang et al. | Bubble budgeting: Throughput optimization for dynamic workloads by exploiting dark cores in many core systems | |
US12223351B2 (en) | Scheduling tasks in a processor | |
Tang et al. | Energy‐Efficient Reliability‐Aware Scheduling Algorithm on Heterogeneous Systems | |
Kanduri et al. | Approximation knob: Power capping meets energy efficiency | |
Kumar et al. | Machine learning based workload balancing scheme for minimizing stress migration induced aging in multicore processors | |
Ekhtiyari et al. | A temperature-aware and energy-efficient fuzzy technique to schedule tasks in heterogeneous MPSoC systems | |
Senapati et al. | PRESTO: A penalty-aware real-time scheduler for task graphs on heterogeneous platforms | |
Lammie et al. | Scheduling grid workloads on multicore clusters to minimize energy and maximize performance | |
Alsafrjalani et al. | Dynamic scheduling for reduced energy in configuration-subsetted heterogeneous multicore systems | |
Gajaria et al. | ARC: DVFS-aware asymmetric-retention STT-RAM caches for energy-efficient multicore processors | |
Garg et al. | Technology-driven limits on runtime power management algorithms for multiprocessor systems-on-chip | |
Baital et al. | Energy efficient dynamic scheduling of dependent tasks for multi‐core real‐time systems using delay techniques | |
Rodríguez et al. | A thermal-aware approach for DVFS-enabled multi-core architectures | |
Salamy | Energy-aware schedules under chip reliability constraint for multi-processor systems-on-a-chip | |
Sheikh et al. | Fast algorithms for simultaneous optimization of performance, energy and temperature in DAG scheduling on multi-core processors | |
Hua et al. | Probabilistic design of multimedia embedded systems | |
Huang et al. | Transmuting coprocessors: dynamic loading of FPGA coprocessors | |
Kohútka et al. | RED-based scheduler on chip for mixed-criticality real-time systems | |
Ranjbar et al. | Preliminaries and Related Work | |
Zhao et al. | Adaptive selection and clustering of partial reconfiguration modules for modern FPGA design flow |