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Ali et al., 2013 - Google Patents

Accurate timing analysis of combinational logic cells engine using adaptive technique based on current source model

Ali et al., 2013

Document ID
17893121487208576052
Author
Ali A
Hussein A
El-Rouby A
Mahmoud M
Wassal A
Publication year
Publication venue
2013 Saudi International Electronics, Communications and Photonics Conference

External Links

Snippet

As the usage of very large scale integration (VLSI) in computers continues to increase, debugging of timing problems on actual hardware becomes more and more difficult. The post-layout gate-level simulation constitutes a critical design step for timing closure. The …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G06F17/5031—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
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    • G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • G—PHYSICS
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    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
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