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Roshanghias et al., 2022 - Google Patents

High-Resolution Printing of Redistribution Layers for Fan-Out Wafer-Level Packaging by using Ultra-Precise Micro-deposition Technology

Roshanghias et al., 2022

Document ID
17436587906172084084
Author
Roshanghias A
Dreissigacker M
Gradzka-Kurzaj I
Binder A
Ramelow M
Witczak Ĺ
Braun T
Publication year
Publication venue
2022 IEEE 9th Electronics System-Integration Technology Conference (ESTC)

External Links

Snippet

Implementing Additively Manufactured Redistribution Layers (AM-RDL) for Fan-Out Wafer- Level Packaging (FOWLP) has spurred interest recently. Especially for MEMS FOWLP, where the standard fabrication of RDLs faced challenges to provide conformity to 3D …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector

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