[go: up one dir, main page]

Latif et al., 2011 - Google Patents

A novel topology-independent router architecture to enhance reliability and performance of networks-on-chip

Latif et al., 2011

Document ID
1727763888271133469
Author
Latif K
Rahmani A
Nigussie E
Tenhunen H
Seceleanu T
Publication year
Publication venue
2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

External Links

Snippet

We present the partial virtual-channel sharing (PVS) NoC architecture which reduces the impact of fault on system performance and can also tolerate the faults on routing logic. A fault in one component makes the fault-free connected components out of use and this in …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems
    • H04L12/56Packet switching systems
    • H04L12/5601Transfer mode dependent, e.g. ATM
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/25Routing or path finding through a switch fabric
    • H04L49/253Connections establishment or release between ports
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/10Switching fabric construction
    • H04L49/109Switching fabric construction integrated on microchip, e.g. switch-on-chip
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/22Alternate routing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/30Peripheral units, e.g. input or output ports
    • H04L49/3009Header conversion, routing tables or routing tags
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/15Interconnection of switching modules
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/24Multipath
    • H04L45/245Link aggregation, e.g. trunking
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/12Shortest path evaluation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/60Router architecture
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/06Deflection routing, e.g. hot-potato routing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/50Overload detection; Overload protection
    • H04L49/505Corrective Measures, e.g. backpressure
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored programme computers
    • G06F15/78Architectures of general purpose stored programme computers comprising a single central processing unit
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design

Similar Documents

Publication Publication Date Title
Lotfi-Kamran et al. EDXY–A low cost congestion-aware routing algorithm for network-on-chips
Latif et al. PVS-NoC: Partial virtual channel sharing NoC architecture
Liu et al. Low cost fault-tolerant routing algorithm for networks-on-chip
DiTomaso et al. QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers
Rahmani et al. High-performance and fault-tolerant 3D NoC-bus hybrid architecture using ARB-NET-based adaptive monitoring platform
Ahmed et al. Deadlock-recovery support for fault-tolerant routing algorithms in 3d-noc architectures
Choudhary et al. Performance evaluation of mesh-based NoCs: Implementation of a new architecture and routing algorithm
Jindal et al. Enhancing network-on-chip performance by reusing trace buffers
Neishaburi et al. Reliability aware NoC router architecture using input channel buffer sharing
Neishaburi et al. A fault tolerant hierarchical network on chip router architecture
Latif et al. A novel topology-independent router architecture to enhance reliability and performance of networks-on-chip
Kodi et al. Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs)
Latif et al. Partial virtual channel sharing: a generic methodology to enhance resource management and fault tolerance in networks-on-chip
Rahmani et al. Generic monitoring and management infrastructure for 3D NoC-bus hybrid architectures
Rahmani et al. A stacked mesh 3d noc architecture enabling congestion-aware and reliable inter-layer communication
Agyeman et al. An efficient 2d router architecture for extending the performance of inhomogeneous 3d noc-based multi-core architectures
Wu et al. A novel architecture and routing algorithm for dynamic reconfigurable network-on-chip
Kia et al. A new fault-tolerant and congestion-aware adaptive routing algorithm for regular networks-on-chip
Neishaburi et al. NISHA: A fault-tolerant NoC router enabling deadlock-free interconnection of subnets in hierarchical architectures
Parane et al. LBNoC: design of low-latency router architecture with lookahead bypass for network-on-chip using FPGA
Latif et al. Enhancing performance sustainability of fault tolerant routing algorithms in NoC-based architectures
Manzoor et al. A review of design approaches for enhancing the performance of nocs at communication centric level
Rantala et al. Multi network interface architectures for fault tolerant Network-on-Chip
Rezaei et al. Fault-tolerant 3-D network-on-chip design using dynamic link sharing
Valinataj et al. Enhanced fault-tolerant Network-on-Chip architecture using hierarchical agents