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Dolle et al., 1997 - Google Patents

A 32-b RISC/DSP microprocessor with reduced complexity

Dolle et al., 1997

Document ID
17060073397836373051
Author
Dolle M
Jhand S
Lehner W
Muller O
Schlett M
Publication year
Publication venue
IEEE Journal of Solid-State Circuits

External Links

Snippet

This paper presents a new 32-b reduced instruction set computer/digital signal processor (RISC/DSP) architecture which can be used as a general purpose microprocessor and in parallel as a 16-/32-b fixed-point DSP. This has been achieved by using RISC design …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
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    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
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