VÁSÁRHELYI et al., 2021 - Google Patents
Lecture Notes and Practical Courses on System on Chip (SoC): Materials for Embedded Systems SubjectsVÁSÁRHELYI et al., 2021
View PDF- Document ID
- 16572014775806594135
- Author
- VÁSÁRHELYI J
- BOUZID A
- Publication year
External Links
Snippet
In the previous chapter was mentioned the impact of Moore's law on the evolution of integrated cir‐cuits. There were treated the SOC structures in general and was mentioned that the first system on chip was created by Intel. We have to clarify that this Intel's SOC was …
- 239000000463 material 0 title description 12
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5022—Logic simulation, e.g. for logic circuit operation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/44—Arrangements for executing specific programmes
- G06F9/455—Emulation; Software simulation, i.e. virtualisation or emulation of application or operating system execution engines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/30—Creation or generation of source code
- G06F8/36—Software reuse
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/30—Creation or generation of source code
- G06F8/34—Graphical or visual programming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformations of program code
- G06F8/51—Source to source
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/30—Creation or generation of source code
- G06F8/38—Implementation of user interfaces
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/70—Software maintenance or management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/20—Software design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/20—Handling natural language data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/16—Constructional details or arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/86—Hardware-Software co-design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/74—Symbolic schematics
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/70—Fault tolerant, i.e. transient fault suppression
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Mehta | ASIC/SoC functional design verification | |
US7340693B2 (en) | System for designing re-programmable digital hardware platforms | |
Ashenden et al. | The system designer's guide to VHDL-AMS: analog, mixed-signal, and mixed-technology modeling | |
US7475000B2 (en) | Apparatus and method for managing integrated circuit designs | |
Chu | Embedded SOPC design with NIOS II processor and VHDL examples | |
Salcic | VHDL and FPLDs in digital systems design, prototyping and customization | |
Chu | Embedded SoPC design with NIOS II processor and Verilog examples | |
Wain et al. | An overview of FPGAs and FPGA programming-Initial experiences at Daresbury | |
Mueller et al. | The saturn approach to sysml-based hw/sw codesign | |
Kuhn et al. | A framework for object oriented hardware specification, verification, and synthesis | |
Snider | Advanced Digital System Design using SoC FPGAs | |
Wagner et al. | Strategies for the integration of hardware and software IP components in embedded systems-on-chip | |
Pohl et al. | vMAGIC—automatic code generation for VHDL | |
Borriello et al. | Embedded system co-design: Towards portability and rapid integration | |
Biancolin et al. | Accessible, FPGA resource-optimized simulation of multiclock systems in firesim | |
VÁSÁRHELYI et al. | Lecture Notes and Practical Courses on System on Chip (SoC): Materials for Embedded Systems Subjects | |
US7603656B2 (en) | Methods and systems for modeling concurrent behavior | |
Parab et al. | Hands-on experience with Altera FPGA development boards | |
Cesario et al. | Object-based hardware/software component interconnection model for interface design in system-on-a-chip circuits | |
Maaref | Architecting and Building High-Speed SoCs | |
Mohamed | An Introduction to Heterogeneous SoC Design and Verification “A Conceptual-Level” | |
Parab et al. | How to Build First Nios II System | |
Rodriguez-Navarrete et al. | Cachedia: An Environment for Efficient Cache Verification with Graphic Visualization for Debugging | |
Rivas-Villegas et al. | Graphical framework for automatic generation of custom UVM testbenches in SystemVerilog applied for the validation of a SerDes DUT | |
Lockhart | Constructing Vertically Integrated Hardware Design Methodologies Using Embedded Domain-Specific Languages And Just-In-Time Optimization |