[go: up one dir, main page]

Beierle et al., 2025 - Google Patents

INDIANA-verifying (random) probing security through indistinguishability analysis

Beierle et al., 2025

View PDF
Document ID
16116723392365244504
Author
Beierle C
Feldtkeller J
Guinet A
Güneysu T
Leander G
Richter-Brockmann J
Sasdrich P
Publication year
Publication venue
Annual International Conference on the Theory and Applications of Cryptographic Techniques

External Links

Snippet

While masking is a widely used defense against passive side-channel attacks, its secure implementation in hardware continues to be a manual, complex, and error-prone process. This paper introduces INDIANA, a comprehensive security verification methodology for …
Continue reading at eprint.iacr.org (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/504—Formal methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
    • G06F21/577—Assessing vulnerabilities and evaluating computer system security
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3668—Software testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/55—Detecting local intrusion or implementing counter-measures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7219—Countermeasures against side channel or fault attacks
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N99/00—Subject matter not provided for in other groups of this subclass

Similar Documents

Publication Publication Date Title
Barthe et al. maskverif: Automated verification of higher-order masking in presence of physical defaults
Schneider et al. Leakage assessment methodology: A clear roadmap for side-channel evaluations
Bloem et al. Formal verification of masked hardware implementations in the presence of glitches
US11475168B2 (en) CAD framework for power side-channel vulnerability assessment
Müller et al. Prolead: A probing-based hardware leakage detection tool
Šijačić et al. Towards efficient and automated side-channel evaluations at design time
US9563729B2 (en) Signal transition analysis of a circuit
Shelton et al. Rosita++: Automatic higher-order leakage elimination from cryptographic code
Müller et al. Transitional leakage in theory and practice: Unveiling security flaws in masked circuits
Wang et al. Security by compilation: an automated approach to comprehensive side-channel resistance
Andrikos et al. Location, location, location: Revisiting modeling and exploitation for location-based side channel leakages
Saha et al. Testability based metric for hardware trojan vulnerability assessment
Wu et al. Automated generation of masked nonlinear components: From lookup tables to private circuits
Beierle et al. INDIANA-verifying (random) probing security through indistinguishability analysis
Shao et al. Detection of security vulnerabilities in cryptographic ICs against fault injection attacks based on compressed sensing and basis pursuit
Zhou et al. Leakage detection with Kolmogorov-Smirnov test
Walters et al. Sleak: A side-channel leakage evaluator and analysis kit
Cobb et al. Leakage mapping: A systematic methodology for assessing the side-channel information leakage of cryptographic implementations
Bahrami et al. On the Practicality of Relying on Simulations in Different Abstraction Levels for Pre-silicon Side-Channel Analysis.
Khairallah et al. Hardware implementation of masked SKINNY SBox with application to AEAD
Barthe et al. maskVerif: Automated analysis of software and hardware higher-order masked implementations
Mouris et al. Zk-sherlock: Exposing hardware trojans in zero-knowledge
Sijacic Design Time Evaluation for Side-Channel Attack Resistant Cryptographic Implementations
Kumar et al. Compatibility Graph Assisted Automatic Hardware Trojan Insertion Framework
US20250086288A1 (en) Scalable detection of hardware trojans using atpg-based activation of rare events