[go: up one dir, main page]

Liu et al., 2016 - Google Patents

A dependency-graph based priority assignment algorithm for real-time traffic over NoCs with shared virtual-channels

Liu et al., 2016

Document ID
16198639220190411657
Author
Liu M
Becker M
Behnam M
Nolte T
Publication year
Publication venue
2016 IEEE World conference on factory communication systems (WFCS)

External Links

Snippet

The Network-on-Chip (NoC) is the on-chip interconnection medium of choice for modern massively parallel processors and System-on-Chip (SoC) in general. Fixed-priority based preemptive scheduling using virtual-channels is a solution to support real-time …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Programme initiating; Programme switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4843Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061Partitioning or combining of resources
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems
    • H04L12/56Packet switching systems
    • H04L12/5695Admission control; Resource allocation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic regulation in packet switching networks
    • H04L47/10Flow control or congestion control
    • H04L47/24Flow control or congestion control depending on the type of traffic, e.g. priority or quality of service [QoS]
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/12Shortest path evaluation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic regulation in packet switching networks
    • H04L47/10Flow control or congestion control
    • H04L47/12Congestion avoidance or recovery
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/38Flow based routing
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/30Special provisions for routing multiclass traffic
    • H04L45/302Route determination based on requested QoS
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/25Routing or path finding through a switch fabric
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/02Topology update or discovery
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/04Interdomain routing, e.g. hierarchical routing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic regulation in packet switching networks
    • H04L47/70Admission control or resource allocation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. local area networks [LAN], wide area networks [WAN]
    • H04L12/46Interconnection of networks
    • H04L12/4604LAN interconnection over a backbone network, e.g. Internet, Frame Relay

Similar Documents

Publication Publication Date Title
Indrusiak End-to-end schedulability tests for multiprocessor embedded systems based on networks-on-chip with priority-preemptive arbitration
Liu et al. A dependency-graph based priority assignment algorithm for real-time traffic over NoCs with shared virtual-channels
Al Sheikh et al. Optimal design of virtual links in AFDX networks
Maglione-Mathey et al. Scalable deadlock-free deterministic minimal-path routing engine for infiniband-based dragonfly networks
Sayuti et al. Real-time low-power task mapping in networks-on-chip
Gutiérrez et al. Holistic schedulability analysis for multipacket messages in AFDX networks
Li et al. Deterministic delay analysis of AVB switched Ethernet networks using an extended trajectory approach
Mesidis et al. Genetic mapping of hard real-time applications onto NoC-based MPSoCs—A first approach
Nikolić et al. Real-time analysis of priority-preemptive NoCs with arbitrary buffer sizes and router delays
Indrusiak et al. Buffer-aware bounds to multi-point progressive blocking in priority-preemptive NoCs
Abdallah et al. Wormhole networks properties and their use for optimizing worst case delay analysis of many-cores
Shi et al. Real-time communication analysis with a priority share policy in on-chip networks
Panic et al. Modeling high-performance wormhole NoCs for critical real-time embedded systems
Chen et al. Reduced worst-case communication latency using single-cycle multihop traversal network-on-chip
Liu et al. Tighter time analysis for real-time traffic in on-chip networks with shared priorities
Cattelan et al. Iterative design space exploration for networks requiring performance guarantees
Finzi et al. Breaking vs. solving: Analysis and routing of real-time networks with cyclic dependencies using network calculus
Kurbanov et al. Deadlock-free routing in spacewire onboard network
de Dinechin et al. Feed-forward routing for the wormhole switching network-on-chip of the kalray mppa2 processor
Cardona et al. Noco: Ilp-based worst-case contention estimation for mesh real-time manycores
Liu et al. Buffer-aware analysis for worst-case traversal time of real-time traffic over rra-based nocs
Liu et al. Improved priority assignment for real-time communications in on-chip networks
Liu et al. A tighter recursive calculus to compute the worst case traversal time of real-time traffic over NoCs
Deniziak et al. Co-synthesis of contention-free energy-efficient NOC-based real time embedded systems
Munk et al. Dynamic guaranteed service communication on best-effort networks-on-chip