Chang et al., 2004 - Google Patents
LSI design for MPEG-4 coding systemChang et al., 2004
View PDF- Document ID
- 16163052576748492353
- Author
- Chang Y
- Chao W
- Chen L
- Publication year
- Publication venue
- The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS'04.
External Links
Snippet
This paper presents an LSI design for MPEG-4 video coding. We adopt platform-based architecture with an embedded RISC core and efficient memory organization. A fast motion estimator architecture supporting predictive diamond search and spiral full search with …
- 238000007906 compression 0 abstract description 6
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/43—Hardware specially adapted for motion estimation or compensation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
- G06F1/3234—Action, measure or step performed to reduce power consumption
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
- H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9351003B2 (en) | Context re-mapping in CABAC encoder | |
Liu et al. | A 125$\mu {\hbox {W}} $, Fully Scalable MPEG-2 and H. 264/AVC Video Decoder for Mobile Applications | |
Lin et al. | A 160K gates/4.5 KB SRAM H. 264 video decoder for HDTV applications | |
CN101729893B (en) | MPEG multi-format compatible decoding method based on software and hardware coprocessing and device thereof | |
Yin et al. | A hardware-efficient multi-resolution block matching algorithm and its VLSI architecture for high definition MPEG-like video encoders | |
Xu et al. | A power-efficient and self-adaptive prediction engine for H. 264/AVC decoding | |
Miyama et al. | A sub-mW MPEG-4 motion estimation processor core for mobile video application | |
US9432674B2 (en) | Dual stage intra-prediction video encoding system and method | |
Ismail et al. | High performance architecture for real-time HDTV broadcasting | |
Chang et al. | LSI design for MPEG-4 coding system | |
Senn et al. | Joint DVFS and parallelism for energy efficient and low latency software video decoding | |
Chang et al. | Platform-based MPEG-4 video encoder SOC design | |
Xu et al. | Methods for power/throughput/area optimization of H. 264/AVC decoding | |
Hervigo et al. | A multiprocessors architecture for a HDTV motion estimation system | |
Chang et al. | Platform-based MPEG-4 SOC design for video communications | |
Zheng et al. | An efficient VLSI architecture for motion compensation of AVS HDTV decoder | |
Stabernack et al. | A system on a chip architecture of an H. 264/AVC coprocessor for DVB-H and DMB applications | |
Braly et al. | A configurable H. 265-compatible motion estimation accelerator architecture for realtime 4K video encoding in 65 nm CMOS | |
Nguyen et al. | Implementation of H. 264/AVC encoder on coarse-grained dynamically reconfigurable computing system | |
Kuo et al. | A high-performance low-power H. 264/AVC video decoder accelerator for embedded systems | |
Liu et al. | Design of an H. 264/AVC decoder with memory hierarchy and line-pixel-lookahead | |
Chao et al. | Platform architecture design for MPEG-4 video coding | |
Zheng et al. | A motion vector predictor architecture for AVS and MPEG-2 HDTV decoder | |
Lee et al. | MPEG4 video codec on a wireless handset baseband system | |
Dhahri et al. | An adaptive motion estimator design for high performances H. 264/AVC codec |