Faleiro, 2018 - Google Patents
High Performance Multi-core Transaction Processing via Deterministic ExecutionFaleiro, 2018
View HTML- Document ID
- 15820452768564747786
- Author
- Faleiro J
- Publication year
External Links
Snippet
The increasing democratization of server hardware with multi-core CPUs and large main memories has been one of the dominant hardware trends of the last decade." Bare metal" servers with tens of CPU cores and over 100 gigabytes of main memory have been …
- 230000015654 memory 0 abstract description 79
Classifications
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- G06—COMPUTING; CALCULATING; COUNTING
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- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
- G06F17/30286—Information retrieval; Database structures therefor; File system structures therefor in structured data stores
- G06F17/30345—Update requests
- G06F17/30348—Concurrency control
- G06F17/30359—Pessimistic concurrency control approaches, e.g. locking, multiple versions without time stamps
- G06F17/30362—Locking methods, e.g. distributed locking, locking implementation details
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- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
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- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
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- G06F17/30286—Information retrieval; Database structures therefor; File system structures therefor in structured data stores
- G06F17/30345—Update requests
- G06F17/30348—Concurrency control
- G06F17/30351—Optimistic concurrency control
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- G—PHYSICS
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- G06F17/30286—Information retrieval; Database structures therefor; File system structures therefor in structured data stores
- G06F17/30345—Update requests
- G06F17/30377—Details of updates performed during online database operations; commit processing
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- G—PHYSICS
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- G06F17/30286—Information retrieval; Database structures therefor; File system structures therefor in structured data stores
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- G—PHYSICS
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- G—PHYSICS
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- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Programme synchronisation; Mutual exclusion, e.g. by means of semaphores; Contention for resources among tasks
- G06F9/524—Deadlock detection or avoidance
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- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/466—Transaction processing
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- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30087—Synchronisation or serialisation instructions
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- G—PHYSICS
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
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- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
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