[go: up one dir, main page]

Papadopoulou, 2017 - Google Patents

Variability Analysis and Yield Optimization in Deep-Submicron Mixed-Signal Circuits

Papadopoulou, 2017

View PDF
Document ID
15656902133256088433
Author
Papadopoulou A
Publication year

External Links

Snippet

Scaling of CMOS technology into the deep-submicron regime has made superior device performance and high density possible. However, achieving extreme performance is often limited by an increase in variability due to the aggressive shrinking of dimensions. As …
Continue reading at escholarship.org (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5036Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081Layout analysis, e.g. layout verification, design rule check
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5022Logic simulation, e.g. for logic circuit operation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/505Logic synthesis, e.g. technology mapping, optimisation
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3183Generation of test inputs, e.g. test vectors, patterns or sequence
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78Power analysis and optimization
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N99/00Subject matter not provided for in other groups of this subclass

Similar Documents

Publication Publication Date Title
US8225248B2 (en) Timing, noise, and power analysis of integrated circuits
US7761275B2 (en) Synthesizing current source driver model for analysis of cell characteristics
Arabi et al. Power supply noise in SoCs: Metrics, management, and measurement
US8176454B2 (en) Non-invasive timing characterization of integrated circuits using sensitizable signal paths and sparse equations
KR20190135550A (en) Cell placement and routing using cell level layout dependent stress effects
JP2008523516A (en) Stochastic analysis process optimization for integrated circuit design and manufacturing
US20110040548A1 (en) Physics-based mosfet model for variational modeling
US10713405B2 (en) Parameter generation for semiconductor device trapped-charge modeling
Maricau et al. Efficient variability-aware NBTI and hot carrier circuit reliability analysis
US10747916B2 (en) Parameter generation for modeling of process-induced semiconductor device variation
Wang et al. PROCEED: A Pareto optimization-based circuit-level evaluator for emerging devices
Bhushan et al. CMOS test and evaluation
US8813006B1 (en) Accelerated characterization of circuits for within-die process variations
Olivieri et al. Logic drivers: A propagation delay modeling paradigm for statistical simulation of standard cell designs
Yu et al. Remembrance of transistors past: Compact model parameter extraction using Bayesian inference and incomplete new measurements
JP5569237B2 (en) Information processing apparatus, program, and design support method
Ma et al. Fast cell library characterization for design technology co-optimization based on graph neural networks
Orshansky et al. Direct sampling methodology for statistical analysis of scaled CMOS technologies
Doh et al. A unified statistical model for inter-die and intra-die process variation
Papadopoulou Variability Analysis and Yield Optimization in Deep-Submicron Mixed-Signal Circuits
Bastani et al. Analyzing the risk of timing modeling based on path delay tests.
Bastani et al. Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking-the methodology explained
Tsiena et al. Context-specific leakage and delay analysis of a 65nm standard cell library for lithography-induced variability
Kükner et al. Impact of duty factor, stress stimuli, gate and drive strength on gate delay degradation with an atomistic trap-based BTI model
Liu et al. Fast hierarchical process variability analysis and parametric test development for analog/RF circuits