Hoang et al., 2011 - Google Patents
Power gating multiplier of embedded processor datapathHoang et al., 2011
View PDF- Document ID
- 15482302437524496466
- Author
- Hoang T
- Saseendran V
- Siaudinis D
- Larsson-Edefors P
- Publication year
- Publication venue
- 2011 7th Conference on Ph. D. Research in Microelectronics and Electronics
External Links
Snippet
Leakage power is an important concern in modern electronic designs. To efficiently employ power gating for leakage reduction in embedded processors, the architecture must provide a clear-cut software support for power gating and the power-gated unit must have significant …
- 230000001603 reducing 0 abstract description 31
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
- G06F1/3234—Action, measure or step performed to reduce power consumption
- G06F1/3287—Power saving by switching off individual functional units in a computer system, i.e. selective power distribution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
- G06F1/3234—Action, measure or step performed to reduce power consumption
- G06F1/3237—Power saving by disabling clock generation or distribution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
- G06F1/3234—Action, measure or step performed to reduce power consumption
- G06F1/3296—Power saving by lowering supply or operating voltage
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
- G06F1/3234—Action, measure or step performed to reduce power consumption
- G06F1/324—Power saving by lowering clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/68—Processors
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Srinivasan et al. | Optimizing pipelines for power and performance | |
Magklis et al. | Dynamic frequency and voltage scaling for a multiple-clock-domain microprocessor | |
CN100489734C (en) | Mechanism for estimating and controlling supply voltage variations caused by rate of change of current | |
Constantin et al. | Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment | |
Lee et al. | A variable frequency link for a power-aware network-on-chip (NoC) | |
US8589854B2 (en) | Application driven power gating | |
Tavana et al. | ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scaling | |
Ratković et al. | An overview of architecture-level power-and energy-efficient design techniques | |
De la Guia Solaz et al. | Razor based programmable truncated multiply and accumulate, energy-reduction for efficient digital signal processing | |
Jia et al. | An adaptive clock scheme exploiting instruction-based dynamic timing slack for a GPGPU architecture | |
Samanth et al. | Power reduction of a functional unit using rt-level clock-gating and operand isolation | |
Hoang et al. | Power gating multiplier of embedded processor datapath | |
Azizi et al. | An integrated framework for joint design space exploration of microarchitecture and circuits | |
Tavana et al. | ElasticCore: A dynamic heterogeneous platform with joint core and voltage/frequency scaling | |
Zhang et al. | Adaptive front-end throttling for superscalar processors | |
Giraldo et al. | Leveraging compiler support on vliw processors for efficient power gating | |
Ravi et al. | Aggressive slack recycling via transparent pipelines | |
Wang et al. | Pipeline power reduction through single comparator-based clock gating | |
KR101621760B1 (en) | A pipeline circuit apparatus having asynchronous clock | |
Jayakrishnan et al. | Library pruning and sigma corner libraries for power efficient variation tolerant processor pipelines | |
Marcinek et al. | Enhanced LEON3 low power IP core for DSM technologies | |
Kumar et al. | Learning-based architecture-level power modeling of CPUs | |
Golanbari et al. | Optimizing Datapaths for Near Threshold Computing | |
Ananda Kumar | Learning-based architecture-level power modeling of CPUs | |
Mohyuddin et al. | Deterministic clock gating to eliminate wasteful activity due to wrong-path instructions in out-of-order superscalar processors |