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Pandey et al., 2002 - Google Patents

Reconfiguration technique for reducing test time and test data volume in Illinois scan architecture based designs

Pandey et al., 2002

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Document ID
15343990923821900509
Author
Pandey A
Patel J
Publication year
Publication venue
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)

External Links

Snippet

As the complexity of VLSI circuits is increasing due to the exponential rise in transistor count per chip, testing cost is becoming an important factor in the overall integrated circuit (IC) manufacturing cost. This paper addresses the issue of decreasing test cost by lowering the …
Continue reading at www.researchgate.net (PDF) (other versions)

Classifications

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    • G01MEASURING; TESTING
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    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536Scan chain arrangements, e.g. connections, test bus, analog signals
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