Pandey et al., 2002 - Google Patents
Reconfiguration technique for reducing test time and test data volume in Illinois scan architecture based designsPandey et al., 2002
View PDF- Document ID
- 15343990923821900509
- Author
- Pandey A
- Patel J
- Publication year
- Publication venue
- Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)
External Links
Snippet
As the complexity of VLSI circuits is increasing due to the exponential rise in transistor count per chip, testing cost is becoming an important factor in the overall integrated circuit (IC) manufacturing cost. This paper addresses the issue of decreasing test cost by lowering the …
- 238000000034 method 0 title abstract description 44
Classifications
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
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- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
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