Ma et al., 2017 - Google Patents
Electromigration simulation of flip chip CSP LEDMa et al., 2017
- Document ID
- 15202285495096150283
- Author
- Ma R
- Qin F
- Fan J
- Fan X
- Qian C
- Publication year
- Publication venue
- 2017 18th International Conference on Electronic Packaging Technology (ICEPT)
External Links
Snippet
Chip scale package (CSP) as an advanced technology has been applied to LED lighting devices, besides electromigration (EM) in CSP under high current density has become a critical reliability issue for the future high density microelectronic packaging. In this paper …
- 238000004088 simulation 0 title description 11
Classifications
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L35/00—Thermo-electric devices comprising a junction of dissimilar materials, i.e. exhibiting Seebeck or Peltier effect with or without other thermo-electric effects or thermomagnetic effects; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L35/28—Thermo-electric devices comprising a junction of dissimilar materials, i.e. exhibiting Seebeck or Peltier effect with or without other thermo-electric effects or thermomagnetic effects; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof operating with Peltier or Seebeck effect only
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7511378B2 (en) | Enhancement of performance of a conductive wire in a multilayered substrate | |
| Manno et al. | Microcontact-enhanced thermoelectric cooling of ultrahigh heat flux hotspots | |
| Xu et al. | An assessment of electromigration in 2.5 D packaging | |
| Ma et al. | Electromigration simulation of flip chip CSP LED | |
| Hsieh et al. | Thermo-mechanical simulations for 4-layer stacked IC packages | |
| Dutta et al. | Interface-related reliability challenges in 3-D interconnect systems with through-silicon vias | |
| Xu et al. | Time 0 void evolution and effect on electromigration | |
| Yang et al. | Electromigration and thermomigration behavior of flip chip solder joints in high current density packages | |
| Antonova et al. | Finite elements for electromigration analysis | |
| Ye et al. | Experimental damage mechanics of micro/power electronics solder joints under electric current stresses | |
| Liu et al. | Prediction of electromigration induced voids and time to failure for solder joint of a wafer level chip scale package | |
| ZHANG | Electromigration failure prediction and reliability evaluation of solder bumps for FCBGA package | |
| Shen et al. | Effect of isothermal aging and low density current on intermetallic compound growth rate in lead-free solder interface | |
| Dandu et al. | Finite element modeling on electromigration of solder joints in wafer level packages | |
| Chen et al. | Modeling of electromigration of the through silicon via interconnects | |
| Huang et al. | Current-induced interfacial reactions in Ni/Sn–3Ag–0.5 Cu/Au/Pd (P)/Ni–P flip chip interconnect | |
| Xing et al. | Thermal modeling and characterization of package with through-silicon-vias (TSV) interposer | |
| Dandu et al. | Some remarks on finite element modeling of electromigration in solder joints | |
| Cai et al. | Evaluation of electromigration coupling different physics fields in numerical simulation | |
| Ye et al. | Modeling deformation in microelectronics BGA solder joints under high current density. Part I. Simulation and testing | |
| Yao et al. | Coupling Effect of Electromigration and Joule Heating Induced Failure in Advanced Packaging | |
| Yao et al. | Damage of SAC405 solder joint under PDC | |
| Zhang et al. | Finite element modeling on electromigration of TSV interconnect in 3D package | |
| Chiu et al. | Joule heating effect under accelerated electromigration in flip-chip solder joints | |
| Kanapady et al. | Influence of temperature gradient on electromigration failures in 3D packaging |