Chen et al., 2010 - Google Patents
A hybrid simulated annealing algorithm for nonslicing VLSI floorplanningChen et al., 2010
View PDF- Document ID
- 15130770735274578090
- Author
- Chen J
- Zhu W
- Ali M
- Publication year
- Publication venue
- IEEE Transactions on Systems, Man, and Cybernetics, Part C (Applications and Reviews)
External Links
Snippet
Floorplanning in very large scale integrated-circuit (VLSI) design is the first phase in the process of designing the physical layout of a chip. This makes the floorplanning problem of paramount importance, since it determines the performance, size, yield, and reliability of …
- 238000002922 simulated annealing 0 title abstract description 19
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- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5072—Floorplanning, e.g. partitioning, placement
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- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
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