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Abdelhamid et al., 2024 - Google Patents

SPARKLE: 400 RISC-V GIPS with 1,024 Barrel Processors on a single Datacenter FPGA Card

Abdelhamid et al., 2024

Document ID
15146811427407035399
Author
Abdelhamid R
Valek V
Koch D
Publication year
Publication venue
2024 IEEE 17th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)

External Links

Snippet

SPARKLE is a many-core multi-threaded RISC-V architecture designed for scalable parallel processing. Our implementation on a Xilinx VU9P datacenter-class FPGA comprises 1,024 cores, and 16,384 Harts (Hardware threads), clocking at 400MHz and spanning the entirety …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G06F9/3891—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
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    • G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
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